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Visitor ballanche
Registered: ‎07-01-2015

Need help with KCU105 JESD204 glblclk

Using KCU105 board with Vivado 2016.4. Configure JESD for two lanes with glblclk The following pin assignment worked for Vivado 2016.2 set_property PACKAGE_PIN B1 [get_ports {rxn[1]}] set_property PACKAGE_PIN E3 [get_ports {rxn[0]}] set_property PACKAGE_PIN K5 [get_ports refclk0n] set_property PACKAGE_PIN H5 [get_ports glblclk_n] For Vivado 2016.4, a critical warning shows up during implementation: [Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance i_jd204bv6p0l2sc0_block/inst/i_shared_clocks/i_glblclk_ibufds/DIFFINBUF_INST at H6 (GTHE3_COMMON_X0Y4) since it belongs to a shape containing instance glblclk_p. The shape requires relative placement between i_jd204bv6p0l2sc0_block/inst/i_shared_clocks/i_glblclk_ibufds/DIFFINBUF_INST and glblclk_p that can not be honoured because it would result in an invalid location for glblclk_p. ["C:/S/LTC2124_KCU_150_64_A/systems/2L.00/2L.00.srcs/constrs_1/imports/constrs_1/imports/example_design/jesd204_0_example_design.xdc":365] This warning becomes error during bit file generation. [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 2 out of 175 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: glblclk_p, glblclk_n. Any idea of what is wrong and how to fix it?
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Xilinx Employee
Xilinx Employee
Registered: ‎02-06-2013

Re: Need help with KCU105 JESD204 glblclk



Pins H5 used for global clock is a transceiver reference clock pin and cannot be driven using ibufds as it is dedicated input clock which need to use IBUFDS_GTE3


Use any other normal clock pins to drive this clock.



Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

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