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Visitor komatachia
Visitor
8,312 Views
Registered: ‎04-24-2016

Not able to write or read from MDIO Status register through TEMA

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Hi all,

I have been trying to get a basic system simulated using the TEMAC v9 core, but I am having problems with the MDIO interface. I noticed that the output clock, mdc, never toggles so I looked through the documentation and saw that I needed to write to address 0x500 (MDIO Setup register) and configure the clock and enable bit.

When I was simulating writes to that register, I found that they had no effect at all. Not only that, but when I write and then read from that register, it returns all 0s as if I never wrote there at all.

Does anybody have an idea of what could be wrong? Here's a screenshot of those transactions happening on the AXI lite bus...

ss+(2016-04-24+at+05.31.36).png
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Visitor komatachia
Visitor
14,672 Views
Registered: ‎04-24-2016

Re: Not able to write or read from MDIO Status register through TEMA

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Ok, so I think I've figured it out.

 

ISim pre-synthesis simulation can't simulate the TEMAC. It works during post-synthesis though (once you setup the license). Post-synthesis will not work if there are issues with the license, but it won't tell you that in any obvious way.

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Teacher muzaffer
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Registered: ‎03-31-2012

Re: Not able to write or read from MDIO Status register through TEMA

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could you be having this issue?: https://forums.xilinx.com/t5/Networking-and-Connectivity/Not-able-to-transact-MDIO-via-Host-Interface-for-TMEMAC-V6/td-p/388183
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Visitor komatachia
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Registered: ‎04-24-2016

Re: Not able to write or read from MDIO Status register through TEMA

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I'm not sure because they're using a very different version of the core. In their thread, it looks like they are writing to register 0x340 for configuration instead of 0x500 (which is what is specifically mentioned in the v9 documents). I will try using modelsim though to see if it works.

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Visitor komatachia
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Registered: ‎04-24-2016

Re: Not able to write or read from MDIO Status register through TEMA

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Short update, but I wasn't able to get Modelsim working with the code. Unfortunately the version of Modelsim I have doesn't allow for mixed HDL (the cores libraries seem to force Verilog and the rest of the hdl is in VHDL).

 

Does anybody have any tips on getting this to work?

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Xilinx Employee
Xilinx Employee
8,081 Views
Registered: ‎02-06-2013

Re: Not able to write or read from MDIO Status register through TEMA

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Hi

 

Try simulationg the example design generated with the core and the axi lite controller has the logic to program the registers correctly which you can compart with your logic.

Regards,

Satish

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Visitor komatachia
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Registered: ‎04-24-2016

Re: Not able to write or read from MDIO Status register through TEMA

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Which example design are you referring to?

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Xilinx Employee
Xilinx Employee
7,947 Views
Registered: ‎02-06-2013

Re: Not able to write or read from MDIO Status register through TEMA

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Hi

 

You can refer the standalone temac example design or the Axi ethernet example design(Both have the axi lite controller logic driving the MDIO).

Regards,

Satish

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Visitor komatachia
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Registered: ‎04-24-2016

Re: Not able to write or read from MDIO Status register through TEMA

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Ok, so I think I've figured it out.

 

ISim pre-synthesis simulation can't simulate the TEMAC. It works during post-synthesis though (once you setup the license). Post-synthesis will not work if there are issues with the license, but it won't tell you that in any obvious way.

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