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Observer jqsam1
Observer
502 Views

Rx FCS Errors On 1G/2.5G Pcs Pma and TEMAC

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Hi all. (please refer to the block design i have attached)

We have been experimenting a design which requires 2 SFP running on Copper (RJ45). From what we understand, we have instantiated 2 pair of 1G/2.5G PCS/PMA (SGMII interface) + TEMAC core, which the first pair (SFP1) would be a (Include shared Logic in core) and the second pair (SFP2) would be a (Include shared in example design), since they are in the same GTX Quad. They are configured in physical loopback inside the block design, meaning SFP1's RX would go towards SFP2's TX, vice versa and the 2 pairs are symmetrical. After doing a full bandwidth (Throughput test) using Spirent Tester @ 1G speed each direction, i have encountered Rx FCS Errors (on spirent results page) along the path of SFP2's RX towards SFP1's TX. I have tried isolating and discovered that the Rx FCS errors would occured only on which ever pair of 1G/2.5G PCS/PMA (SGMII interface) + TEMAC core that is a Include shared in example design, i have tested and verified it but cant seem to determine the cause =((((((.

I have done IBERT test on both links ( IBERT opened in example design). There were no BER error, the links were pretty solid. I have tried using LPM mode too, it didnt help =(. We have been facing this issue even before including our own custom ip (rate_limiter_ip). 

The refclk we are using is 125MHz @ 1G speed on a Zynq xc7z030fbg676-2, Vivado 2015.4.
Really need some help here!!!!!

Thanks in advance!!

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Xilinx Employee
Xilinx Employee
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Re: Rx FCS Errors On 1G/2.5G Pcs Pma and TEMAC

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Hi

 

Bit errors can be caused when there is issue with the clocking.

 

When using SGMII interface the default option is to include elastic buffer in the Fabric and in this case you cannot share the rxusrclk and rxusrclk2 from the shared logic in core to shared logic in example design option generated core as you are doing in the shared block diagram.

 

You should follow the recommended clocking in figure 3-16 of below doc

 

https://www.xilinx.com/support/documentation/ip_documentation/gig_ethernet_pcs_pma/v16_1/pg047-gig-eth-pcs-pma.pdf

 

Correct it and let us know the status.

 

 

Regards,

Satish

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Xilinx Employee
Xilinx Employee
800 Views

Re: Rx FCS Errors On 1G/2.5G Pcs Pma and TEMAC

Jump to solution

Hi

 

Bit errors can be caused when there is issue with the clocking.

 

When using SGMII interface the default option is to include elastic buffer in the Fabric and in this case you cannot share the rxusrclk and rxusrclk2 from the shared logic in core to shared logic in example design option generated core as you are doing in the shared block diagram.

 

You should follow the recommended clocking in figure 3-16 of below doc

 

https://www.xilinx.com/support/documentation/ip_documentation/gig_ethernet_pcs_pma/v16_1/pg047-gig-eth-pcs-pma.pdf

 

Correct it and let us know the status.

 

 

Regards,

Satish

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Observer jqsam1
Observer
455 Views

Re: Rx FCS Errors On 1G/2.5G Pcs Pma and TEMAC

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Hi Satish!

I have done the correction by changing the Rxusrclk & Rxusrclk2 's clock source from Rxuserclk_OUT & Rxusrclk2_OUT to it's own RXOUTCLK (through a BUFHCE buffer). It seemed to be working fine now with full throughput! Now i can proceed on with my custom design. Thank you so much!

Best Regards,
Sam

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