UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor tstrickland
Visitor
187 Views
Registered: ‎02-27-2012

SGMII over LVDS in Artix 7 eye monitor maintenance period

In the <>_gpio_sgmii_top.v file generated as part of a SGMII over LVDS implementation using the 1G/2.5G Ethernet PCS/PMA or SGMII IP core, the eye monitor is enabled periodically after initial calibration. The period starts when the previous eye mon is done, and it ends when any bit in the 24-bit eye_mon_timeout register is set. This means a new eye mon will start immediately after the previous one is done. Is that the intended behavior? It seems odd to implement a 24-bit counter that never counts above 2. Should it restart on &eye_mon_timeout instead of |eye_mon_timeout?

always @(posedge clk104) begin // Periodically enable eye monitor
  if (!eye_mon_done) eye_mon_timeout <= 24'h000000;
  else               eye_mon_timeout <= eye_mon_timeout + 1'b1;
end

always @(posedge clk104) eye_mon_timeout_r <= |eye_mon_timeout;

0 Kudos