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Adventurer
Adventurer
8,220 Views
Registered: ‎12-06-2010

SRIO Ref Clock speed for Virtex-7 (415T)

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Hi,

 

I am using Virtex-7 FPGA (415T) and i need to connect  2(x1) SRIO line to FPGA. For that i need to connect ref_clk to the GTH transceivers.

 

Can you please tell me the ref_clk (frequency range)  for the SRIO.

 

Speed of the SRIO lane is 5.0 Gbps. And also my SRIO lane should support 1.25Gbps, 2.5Gbps, and 3.125Gbps.

 

 

Regards,

Magalingam

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Xilinx Employee
Xilinx Employee
15,101 Views
Registered: ‎02-06-2013

Re: SRIO Ref Clock speed for Virtex-7 (415T)

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Hi

 

You can find the reference clocks from the PG007 and snapshot below .srio clk.png

Regards,

Satish

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Xilinx Employee
Xilinx Employee
15,102 Views
Registered: ‎02-06-2013

Re: SRIO Ref Clock speed for Virtex-7 (415T)

Jump to solution

 

Hi

 

You can find the reference clocks from the PG007 and snapshot below .srio clk.png

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
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