Hi~~~
I'm using SRIO transmit data from FPGA to DSP. I find the last 8 bytes data of SRIO package get lost (for the SRIO IP gets a 64-bits interface, it means that the data of the last clock in the package get lost).
I will show some images:
1. First I initialize DSP's memory data into 0xAF (just make DSP's memory into especial data).
2.Then start the SRIO (ignore the noise). This is what I get form the DSP. The image is 512*512, 8-bits grayscale. And there are tow vertical lines in the iamge, and that is where the last 8 bytes of the SRIO package.
From the DSP's memory browser, the memory of the last 8 bytes of SRIO package are never changed, it's still 0xAF.
3. Let's see the FPGA's ILA:
The steps are:
Send head - send 256 bytes data - send head - send 256 bytes data - ........(until the whole image is sent) - send doorbell. From the ILA, let's focus on tvalid and tx_cnt. The tvalid is form SRIO-IP, and tx_cnt is the count of data (not included head and doorbell). With tvalid and tx_cnt, we can see that FPGA has sent the head and 256 bytes data, but DSP can't receive the last 8 bytes data (the last clock of SRIO IP's data).
Thank you very much for reading my question~~~
