UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor parampampam
Visitor
9,442 Views
Registered: ‎11-26-2014

SelectIO for DVI receiving

Hello,

 

I want to use SelectIO IP for DVI receiving. But I have two problems:

1. I customized SelectIO block and put it into my top Verilog design:

module system
(
    input clock,
    input reset,
    
    // DVI in stuff
    input dvi_in_clock_n,
    input dvi_in_clock_p,
    input dvi_in_red_n,
    input dvi_in_red_p,
    input dvi_in_green_n,
    input dvi_in_green_p,
    input dvi_in_blue_n,
    input dvi_in_blue_p,
    
    output [29:0] data_in_to_device
);

    dvi_receiver_0 dr0
    (
        .clk_in_p(dvi_in_clock_p),
        .clk_in_n(dvi_in_clock_n),
        .data_in_from_pins_p({dvi_in_red_p, dvi_in_green_p, dvi_in_blue_p}),
        .data_in_from_pins_n({dvi_in_red_n, dvi_in_green_n, dvi_in_blue_n}),
        
        .data_in_to_device(data_in_to_device)
    );

endmodule

Then, I opened elaborated design but couldn't assign pins because field "Neg Diff Pair" was locked (look at my screenshot). As well I don't understand, why does this IP has differential inputs? I thought we don't have diff signals inside FPGA design.

 

2. I couldn't find VSYNC and HSYNC outputs in SelectIO IP. Where can I take these signals? What the structure does data_in_to_device bus have? I couldn't find this information in SelectIO doc.

 

Thanks in advance.

Скриншот 2015-01-30 15.10.16.png
0 Kudos
3 Replies
Xilinx Employee
Xilinx Employee
9,381 Views
Registered: ‎07-31-2012

Re: SelectIO for DVI receiving

Hi,

 

The SelectIO IP does not implement a full DVI interface with protocols. It is just a physical interconnect which has just the DVI related signals using the Xilinx IO's with their IO standards. 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
0 Kudos
Xilinx Employee
Xilinx Employee
9,376 Views
Registered: ‎02-06-2013

Re: SelectIO for DVI receiving

Hi

 

Check below XAPP's which has useful info on implementing this

 

http://www.xilinx.com/support/documentation/application_notes/xapp495_S6TMDS_Video_Interface.pdf

 

http://www.xilinx.com/support/documentation/application_notes/xapp460.pdf

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
Tags (1)
0 Kudos
Visitor parampampam
Visitor
9,293 Views
Registered: ‎11-26-2014

Re: SelectIO for DVI receiving

>The SelectIO IP does not implement a full DVI interface with protocols

Ok. Where could I read about output data format of SelectIO in DVI receiver mode?

 

And what is about connection SelectIO to pins of my chip? I cannot still connect differential ports of this IP to differential pins of the chip.

0 Kudos