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Virtex6: Placement of TMAC block and GTX for 1000BASE-X

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Visitor
Posts: 7
Registered: ‎06-02-2017
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Virtex6: Placement of TMAC block and GTX for 1000BASE-X

Hi,

 

I have a specific question about the placement of the TMAC block and the GTX transceiver (for 1000BASE-X as PHY interface).

 

The UG800 (https://www.xilinx.com/support/documentation/ip_documentation/v6_emac/v2_3/ug800_v6_emac.pdf) recommends (p.145):

"For 1000BASE-X PCS/PMA or SGMII physical interface configurations, use the serial transceiver located closest to the V6EMAC block."

 

My question: is this necessary (will there be timing problems is the components are placed differently) or is this “just” a recommendation? Is it enough to correctly constrain TXOUTCLK from the GTX (see: UG800 p.139) for the interface between MAC and GTX?

 

The problem is: we have to use another GTX transceiver (due to the PCB layout). (More precisely: on xc6vlx130t-ff1156 we use TEMAC_X0Y0 and GTXE1_X0Y0, with are in completely different clocking regions)

 

We observe unreliable behaviour in practice. However, the timing report is not giving an error.

 

Best regards

Henning

 

 


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Moderator
Posts: 3,217
Registered: ‎02-06-2013

Re: Virtex6: Placement of TMAC block and GTX for 1000BASE-X

Hi

 

Yes the recommendation is to ease the timing and if timing is clean then it's ok to use the transceivers which are not closer.

 

What is the unreliable behavior you are seeing with the cores? 

Regards,

Satish

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Moderator
Posts: 3,217
Registered: ‎02-06-2013

Re: Virtex6: Placement of TMAC block and GTX for 1000BASE-X

Hi

 

Yes the recommendation is to ease the timing and if timing is clean then it's ok to use the transceivers which are not closer.

 

What is the unreliable behavior you are seeing with the cores? 

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
Visitor
Posts: 7
Registered: ‎06-02-2017

Re: Virtex6: Placement of TMAC block and GTX for 1000BASE-X

Hi,

 

"What is the unreliable behavior you are seeing with the cores? "

The design stops working (sending Ethernet packets) after approx. 6 seconds. Licensing issues (e.g. eval license of TMAC) are very unlikely. In the functional simulation the design works fine.

 

Best regards

Henning

Moderator
Posts: 3,217
Registered: ‎02-06-2013

Re: Virtex6: Placement of TMAC block and GTX for 1000BASE-X

Hi

 

Are you using the Embedded MAC or soft MAC in your design?

 

Does giving a reset clears the issue or you need to reprogram the bit file to make the design work again?

 

Where exactly is core getting struck is this at TX tready or RX data or between the MAC and the BASE-X core.

Regards,

Satish

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