UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor leosap
Visitor
118 Views
Registered: ‎02-16-2013

XSIM simulation never come back from run

image.png

Hello.

I am trying to simulate Axi-Lite interface to aurora core. And  without core it I loopback stream interfaces everything is working fine. However when I connect Aurora core and try to simulate it it go to infinite loop and never return. I tryed to step through and I got same result. I captured it in attached picture. For Aurora core I am using loopback set to "010".  Let me know what additional information could be useful to resolve issue.

Thank you

0 Kudos
1 Reply
Moderator
Moderator
20 Views
Registered: ‎05-02-2017

Re: XSIM simulation never come back from run

 

hi @leosap,

 

I believe  and assume your uisng AXIchip2chip IP core with Aurora linking and issue is seen in simulation .

to debug this can you please let me know what Aurora confiuration is it 8b/10b or 64b/66b .

 

The most effective method of debugging this condition is to view the signals from one instance of the serial transceivers that is not working.

Make sure that the serial transceiver reference clock and user clocks are all toggling.

 Check to see that txoutclk from the serial transceiver wrapper is toggling. If not, it might take longer for the PMA to finish locking. Wait for lane up and channel up. It might take even longer for simplex designs.

Make sure that txn and txp are toggling. If not, make sure to wait long enough and ensure that the TX signal is not being driven by another signal. Check the pll_not_locked signal in the design. If it is held active-High, the Aurora module is unable to initialize.

 Be sure the power_down signal is not asserted. • If you assert rx_reset while using Timer mode and simplex configuration, you should also assert tx_reset to ensure that the core transmits the required initialization patterns for the rx_lane_up and rx_channel_up to come up

Regards
Chandra sekhar
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if solution provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos