UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
8,344 Views
Registered: ‎09-23-2011

aurora core unstable lane up

I've generated GTP seperately for aurora 8b/10b protocol on 3 Gbps and 150 MHZ refclk.

I'm having issues with lane up and channel up. lane up is de-asserted and chennel up is never high.

It looks like the rxreset is triggered because of missing SP sequence.

and on the TX side the generate SCP is never asserted. This is using the same example design and jsut replacing the GTP cores.Aurora8b/10b is configured for simplex single lane 4 byte.

 

 

 

 

0 Kudos
2 Replies
Explorer
Explorer
8,343 Views
Registered: ‎09-23-2011

Re: aurora core unstable lane up

Facing this in the simulation and using aurora example tb and designs (replaced GTP)

0 Kudos
Moderator
Moderator
8,315 Views
Registered: ‎02-16-2010

Re: aurora core unstable lane up

Is this with Simplex? if Yes, can you assert reset on Simplex Tx and check if Simplex Rx has channel up asserted.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos