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Observer alexlee256
Registered: ‎02-04-2015

gtwizard example design DONT_TOUCH attribute required

I am trying to build on a gtwizard ultrascale example design by adding my own modules to the toplevel.

I noticed that the toplevel wrapper contains (* DONT_TOUCH = "TRUE" *) decalrations at every module instantiation, as shown below:

  // PRBS-based data stimulus module for transceiver channel 0
  (* DONT_TOUCH = "TRUE" *)
  gtwizard_ultrascale_0_example_stimulus_raw example_stimulus_inst0 (
    .gtwiz_reset_all_in          (hb_gtwiz_reset_all_int),
    .gtwiz_userclk_tx_usrclk2_in (hb0_gtwiz_userclk_tx_usrclk2_int),
    .gtwiz_userclk_tx_active_in  (hb0_gtwiz_userclk_tx_active_int),
    .txdata_out                  (hb0_gtwiz_userdata_tx_int)

 My problem is that I want to run my own modules off the same clock 'hb0_gtwiz_userclk_tx_usrclk2_int', but unless I include the (* DONT_TOUCH = "TRUE" *) attribute, then all the inputs to my module are tied to ground in the post-synthesis schematic.

I feel sure that it isn't the correct approach to put (* DONT_TOUCH = "TRUE" *) everywhere, as optimisation in the correct place is helpful.

I would be grateful if somebody could shed some light as to why this attribute is required in the first place, and how I can work around it.

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Xilinx Employee
Xilinx Employee
Registered: ‎10-24-2013

Re: gtwizard example design DONT_TOUCH attribute required

Moving to correct board.
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Xilinx Employee
Xilinx Employee
Registered: ‎02-06-2013

Re: gtwizard example design DONT_TOUCH attribute required



Don't touch attribute will be used in the vhdl files if the particular module ports are not connected to the top level ports or only used based on the configurations like prbs testing in this case where the tool will try to optimize them otherwise.


If you logic modules have atlease one of the control input or outputs driving the top ports then they will not optimisez by the tool and no need to use dont touch attributes.





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