UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Newbie typhooncome
Newbie
3,271 Views
Registered: ‎01-18-2010

i can't get usrclk in the aurora example

I generate a roketio project with core generator of aurora protocol, and implement on the 5vlx30t, GTP clk is 125MHz, but i can't get the userclk with chipscope, it seems that PLL can not lock the clock;

but with the same port of the ibert core, it  display the clock is locked and link is fine.

 

my questions is what difference between aurora core and ibert core? what is requirement of gtp clock, why ibert core can work but aurora core not work??

0 Kudos
2 Replies
Visitor xaviergr
Visitor
3,064 Views
Registered: ‎02-20-2010

Re: i can't get usrclk in the aurora example

I have the same problem. Simulating the provided aurora example on modelsim, user_clk (or tx_out_clk) never toggles (while the refference clock toggles as it should).

If I start to toggle user_clk manually the IP seems to start working but clearly something is wrong.

0 Kudos
Visitor xaviergr
Visitor
3,056 Views
Registered: ‎02-20-2010

Re: i can't get usrclk in the aurora example

I managed to solve the problem myself (once again out of pure luck). The aurora "Getting started guide" on the "Simulating the Example Design" chapter states the steps in order to simulate the example on ModelSim. While I followed the steps described the example design wouldn't not be simulated successfully.

 

In order to make it work I had to build the libraries using XPS (Simulation -> Compile Simulation Libraries), then edited modelsim.ini to add them. For some reason libraries compiled from ISE didn't work.

0 Kudos