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Visitor beamspace
Registered: ‎02-02-2017

jesd204b ip design

I'm currently design a TX/RX jesd204b interfance now and I have two questions:


1st is that for the jesd204 ip, there are AXI ports and non-AXI ports. If I just use non-AXI data transfer, what should I do with all AXI ports? Or I have to use AXI interface with it?


2nd is that the example design uses jesd204 and jesd204_PHY as a combination of design. What I'm thinking is that maybe I can use a transceiver core to replace jesd204_PHY core ? (similar to FMC144 reference design, which is provided by 4DSP.) 





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Xilinx Employee
Xilinx Employee
Registered: ‎02-06-2013

Re: jesd204b ip design



You should be driving both the axi and non AXi interface signals as per the timing diagrams mentioned in PG066 for successful transmission of data.


Refer the example design delivered to know more on how the intefaces are driven


Why do you want to remove the PHY core and manually design a transceiver wizard as it needs extra logic to interface to the JESD core and it complicate things.



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