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527 Views
Registered: ‎01-27-2016

jesd204b reset connections

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I am creating a JESD204B design to interface with the AD9371. I am creating separate two channel TX and RX JESD204B cores with separate two channel JESD204B PHY cores. I am using IP Integrator to create the block diagram following the example provided in Figure 3-20 of the pg066 JESD204 LogiCore IP User Guide. I was able to complete the design, but I got some warnings about tx_sys_reset and rx_sys_reset signals on the JESD204_PHY core, the rx_reset signal on the JESD204_RX core, and the tx_reset signals not being driven. I had connected them as shown in the figure, but they are all inputs. For now I have added a signal port to provide the input signal to all the reset signals mentioned previously. Is there a better way to connect them or is providing a common reset signal a good way to connect them. Thanks.

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Xilinx Employee
Xilinx Employee
684 Views
Registered: ‎10-19-2011

Re: jesd204b reset connections

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Hi @centercitybill,

 

these signals are the main reset inputs of the IP cores. It depends on your system how to control them. Either you have an external input to the FPGA that is used for it (through a controller) or you have the controller inside the FPGA.

You could check in the simulation testbench of the example design how they can be driven.

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2 Replies
Xilinx Employee
Xilinx Employee
685 Views
Registered: ‎10-19-2011

Re: jesd204b reset connections

Jump to solution

Hi @centercitybill,

 

these signals are the main reset inputs of the IP cores. It depends on your system how to control them. Either you have an external input to the FPGA that is used for it (through a controller) or you have the controller inside the FPGA.

You could check in the simulation testbench of the example design how they can be driven.

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Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
459 Views
Registered: ‎01-27-2016

Re: jesd204b reset connections

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Thanks. I will take a look at the test bench.

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