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Contributor
Contributor
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Registered: ‎05-11-2018

xc7a100tfgg676-2 and 5 GTP Transceivers

We are trying to convert a design from a xc7k325 FPGA to a xc7a100tfgg676-2 device.  Part of our design implements a 5 transceiver IP (4 data, 1 clock) for LVDS communication 7:1 bit rate ratio between the data lines and the clock.  We started with the xc7a200tffg1156 device and did not have any trouble creating the IP, but when we switched to the xc7a100tfgg676 device I am unable to generate a 5 GTP transceiver design.  The xc7a100tfgg676 device has 8 GTP transceivers (banks 213,216). 

How come I am unable to generate a 5 transceiver design? 

Is this because the two banks are on opposite sides of the FPGA?

If I am unable to generate a 5 transceiver design, can I realisitically create a 4 transceiver design for the 4 data lines and a 1 transceiver design for the clock and have them connect to the same target and function properly?  Would I need to do anything special to synchronize the two blocks?

I have attached a simple illustration of our current design.

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