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Registered: ‎01-12-2019

Create Overlay from Verilog / VHDL ?

I am new to pynq board, however I have worked with FPGAs before. Is there a way I can create a design in Vivado using an HDL (Verilog / VDL / SV) and convert it into an overlay to be used through the python interface in PYNQ boards? Can you help me with a link / step by step instrutions?

 

I searched for a few days and all I could find was creating an overlay with C. For me it looks like a high level language such as C is ambiguous, inefficient and unsuitable for hardware module design. Is there a way to do it with a HDL instead?

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Registered: ‎11-09-2015

Re: Create Overlay from Verilog / VHDL ?

Hi @abarajithan11 ,

First note that there is a forums dedicated to pynq. You might want to ask your pynq  related question on it and not on the xilinx forums:

http://www.pynq.io/support.html

Then yes, you can create your own overlay in VHDL/Verilog/SV. The overlay is just a btstream with a TCL file. The steps are documented here:

https://pynq.readthedocs.io/en/latest/overlay_design_methodology.html

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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