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Observer
Observer
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Registered: ‎02-02-2019

uart need helps

hey guys

I wrote  a project for a lathe and other sections it needs to use UART to show that it works after that I wrote a Uart for this project but ISE takes several errors and then the Uart didn't work in my project could you please chech my project and tell whats my wrong

enc5

module enc5(clk, databus,sel,wr,oe,
quadA1, quadB1, quadZ1,
quadA2, quadB2, quadZ2,
quadA3, quadB3, quadZ3,
quadA4, quadB4, quadZ4,
quadA5 ,quadB5, quadZ5,
quadA6 ,quadB6, quadZ6,
);

input oe,wr,clk;
input [2:0] sel;
inout [7:0] databus;

//BUFGP gclk (.I(aclk),.O(clk)) ;

input quadA1, quadB1, quadZ1;
input quadA2, quadB2, quadZ2;
input quadA3, quadB3, quadZ3;
input quadA4, quadB4, quadZ4;
input quadA5, quadB5, quadZ5;
input quadA6, quadB6, quadZ6;

//reg pquadA1;


reg [2:0] quadA1_delayed, quadB1_delayed;
reg [2:0] quadA2_delayed, quadB2_delayed;
reg [2:0] quadA3_delayed, quadB3_delayed;
reg [2:0] quadA4_delayed, quadB4_delayed;
reg [2:0] quadA5_delayed, quadB5_delayed;
reg [2:0] quadA6_delayed, quadB6_delayed;

reg [2:0] quadZ1_delayed;
reg [2:0] quadZ2_delayed;
reg [2:0] quadZ3_delayed;
reg [2:0] quadZ4_delayed;
reg [2:0] quadZ5_delayed;
reg [2:0] quadZ6_delayed;

//reg cap1received,cap2received,cap3received,cap4received,cap5received,cap6received;

//reg [3:0] encoder_pre;
//reg encoder_clock;

//always @ (posedge clk)
//begin
// encoder_pre<=encoder_pre+1;
// if (encoder_pre==4'b1001)
// begin
// encoder_clock<=~encoder_clock;
// encoder_pre<=0;
// end
//end

reg [3:0] encoder_pre;
reg encoder1_clk;
reg encoder2_clk;
reg encoder3_clk;
reg encoder4_clk;
reg encoder5_clk;
reg encoder6_clk;
//reg encoder1_reset;
//reg encoder2_reset;
//reg encoder3_reset;
//reg encoder4_reset;
//reg encoder5_reset;
//reg encoder6_reset;

 


always @(posedge encoder1_clk) quadA1_delayed <= {quadA1_delayed[1:0], quadA1};
always @(posedge encoder2_clk) quadA2_delayed <= {quadA2_delayed[1:0], quadA2};
always @(posedge encoder3_clk) quadA3_delayed <= {quadA3_delayed[1:0], quadA3};
always @(posedge encoder4_clk) quadA4_delayed <= {quadA4_delayed[1:0], quadA4};
always @(posedge encoder5_clk) quadA5_delayed <= {quadA5_delayed[1:0], quadA5};
always @(posedge encoder6_clk) quadA6_delayed <= {quadA6_delayed[1:0], quadA6};

always @(posedge encoder1_clk) quadB1_delayed <= {quadB1_delayed[1:0], quadB1};
always @(posedge encoder2_clk) quadB2_delayed <= {quadB2_delayed[1:0], quadB2};
always @(posedge encoder3_clk) quadB3_delayed <= {quadB3_delayed[1:0], quadB3};
always @(posedge encoder4_clk) quadB4_delayed <= {quadB4_delayed[1:0], quadB4};
always @(posedge encoder5_clk) quadB5_delayed <= {quadB5_delayed[1:0], quadB5};
always @(posedge encoder6_clk) quadB6_delayed <= {quadB6_delayed[1:0], quadB6};

always @(posedge encoder1_clk) quadZ1_delayed <= {quadZ1_delayed[1:0], quadZ1};
always @(posedge encoder2_clk) quadZ2_delayed <= {quadZ2_delayed[1:0], quadZ2};
always @(posedge encoder3_clk) quadZ3_delayed <= {quadZ3_delayed[1:0], quadZ3};
always @(posedge encoder4_clk) quadZ4_delayed <= {quadZ4_delayed[1:0], quadZ4};
always @(posedge encoder5_clk) quadZ5_delayed <= {quadZ5_delayed[1:0], quadZ5};
always @(posedge encoder6_clk) quadZ6_delayed <= {quadZ6_delayed[1:0], quadZ6};

 

//always @(posedge clk) pquadA1<=quadA1;

wire count1_enable = quadA1_delayed[1] ^ quadA1_delayed[2] ^ quadB1_delayed[1] ^ quadB1_delayed[2];
wire count2_enable = quadA2_delayed[1] ^ quadA2_delayed[2] ^ quadB2_delayed[1] ^ quadB2_delayed[2];
wire count3_enable = quadA3_delayed[1] ^ quadA3_delayed[2] ^ quadB3_delayed[1] ^ quadB3_delayed[2];
wire count4_enable = quadA4_delayed[1] ^ quadA4_delayed[2] ^ quadB4_delayed[1] ^ quadB4_delayed[2];
wire count5_enable = quadA5_delayed[1] ^ quadA5_delayed[2] ^ quadB5_delayed[1] ^ quadB5_delayed[2];
wire count6_enable = quadA6_delayed[1] ^ quadA6_delayed[2] ^ quadB6_delayed[1] ^ quadB6_delayed[2];


wire count1_direction = quadA1_delayed[1] ^ quadB1_delayed[2];
wire count2_direction = quadA2_delayed[1] ^ quadB2_delayed[2];
wire count3_direction = quadA3_delayed[1] ^ quadB3_delayed[2];
wire count4_direction = quadA4_delayed[1] ^ quadB4_delayed[2];
wire count5_direction = quadA5_delayed[1] ^ quadB5_delayed[2];
wire count6_direction = quadA6_delayed[1] ^ quadB6_delayed[2];


wire capture1=quadZ1_delayed[1] ^ quadZ1_delayed[2];
wire capture2=quadZ2_delayed[1] ^ quadZ2_delayed[2];
wire capture3=quadZ3_delayed[1] ^ quadZ3_delayed[2];
wire capture4=quadZ4_delayed[1] ^ quadZ4_delayed[2];
wire capture5=quadZ5_delayed[1] ^ quadZ5_delayed[2];
wire capture6=quadZ6_delayed[1] ^ quadZ6_delayed[2];

reg [31:0] count1,cap1;
reg [31:0] count2,cap2;
reg [31:0] count3,cap3;
reg [31:0] count4,cap4;
reg [31:0] count5,cap5;
reg [31:0] count6,cap6;
//reg [31:0] timer;
//reg [7:0] pretimer;
reg [31:0] ll;
reg [7:0] dataout;

 

 

always @(posedge clk)
begin
encoder_pre<=encoder_pre+1;
if (encoder_pre==4'b1001)
begin
encoder_pre<=0;
encoder1_clk<=~encoder1_clk;
encoder2_clk<=~encoder2_clk;
encoder3_clk<=~encoder3_clk;
encoder4_clk<=~encoder4_clk;
encoder5_clk<=~encoder5_clk;
encoder6_clk<=~encoder6_clk;
end
if (!wr)
begin
if (databus[7:3]==5'b00000)
begin
if (databus[2:0]==3'b001)
ll<=count1;
else if (databus[2:0]==3'b010)
ll<=count2;
else if (databus[2:0]==3'b011)
ll<=count3;
else if (databus[2:0]==3'b100)
ll<=count4;
else if (databus[2:0]==3'b101)
ll<=count5;
else if (databus[2:0]==3'b110)
ll<=count6;
end

else if (databus[7:3]==5'b00001)
begin
if (databus[2:0]==3'b001)
ll<=cap1;
else if (databus[2:0]==3'b010)
ll<=cap2;
else if (databus[2:0]==3'b011)
ll<=cap3;
else if (databus[2:0]==3'b100)
ll<=cap4;
else if (databus[2:0]==3'b101)
ll<=cap5;
else if (databus[2:0]==3'b110)
ll<=cap6;
end

// else if (databus[7:3]==5'b00010)
// begin
// if (databus[2:0]==3'b001)
// cap1received<=0;
// else if (databus[2:0]==3'b010)
// cap2received<=0;
// else if (databus[2:0]==3'b011)
// cap3received<=0;
// else if (databus[2:0]==3'b100)
// cap4received<=0;
// else if (databus[2:0]==3'b101)
// cap5received<=0;
// else if (databus[2:0]==3'b110)
// cap6received<=0;
// end

// else if (databus[7:3]==5'b00011)
// begin
// if (databus[2:0]==3'b001)
// encoder1_reset<=1;
// else if (databus[2:0]==3'b010)
// encoder2_reset<=1;
// else if (databus[2:0]==3'b011)
// encoder3_reset<=1;
// else if (databus[2:0]==3'b100)
// encoder4_reset<=1;
// else if (databus[2:0]==3'b101)
// encoder5_reset<=1;
// else if (databus[2:0]==3'b110)
// encoder6_reset<=1;
// end
//
// else if (databus[7:3]==5'b00100)
// ll<={cap6received,cap5received,
// cap4received,cap3received,
// cap2received,cap1received};
// else if (databus[7:3]==5'b00101)
// ll<=timer;

// else if (databus[7:3]==5'b00101)
// begin
// encoder1_reset<=0;
// encoder2_reset<=0;
// encoder3_reset<=0;
// encoder4_reset<=0;
// encoder5_reset<=0;
// encoder6_reset<=0;
// end

end

// pretimer<=pretimer+1;
// if (pretimer==8'b01100011)
// begin
// pretimer<=8'b00000000;
// timer<=timer+1;
// end

 

if (sel==3'b000)
dataout=ll[7:0];
else if (sel==3'b001)
dataout=ll[15:8];
else if (sel==3'b010)
dataout=ll[23:16];
else if (sel==3'b011)
dataout=ll[31:24];
// else if (sel==3'b101)
// dataout=in24[15:8];
// else if (sel==3'b110)
// dataout=in24[23:16];
end

 

always @(negedge encoder1_clk)
begin
if(count1_enable)
begin
if(count1_direction) count1<=count1+1; else count1<=count1-1;
end
if (capture1)
begin
cap1<=count1;
// cap1received<=1;
end
// if (encoder1_reset)
// begin
// count1<=0;
// end

end


always @(negedge encoder2_clk)
begin
if(count2_enable)
begin
if(count2_direction) count2<=count2+1; else count2<=count2-1;
end
if (capture2)
begin
cap2<=count2;
// cap2received<=1;
end
// if (encoder2_reset)
// begin
// count2<=0;
// end
end


always @(negedge encoder3_clk)
begin
if(count3_enable)
begin
if(count3_direction) count3<=count3+1; else count3<=count3-1;
end
if (capture3)
begin
cap3<=count3;
// cap3received<=1;
end
// if (encoder3_reset)
// begin
// count3<=0;
// end
end

always @(negedge encoder4_clk)
begin
if(count4_enable)
begin
if(count4_direction) count4<=count4+1; else count4<=count4-1;
end
if (capture4)
begin
cap4<=count4;
// cap4received<=1;
end
// if (encoder4_reset)
// begin
// count4<=0;
// end
end

always @(negedge encoder5_clk)
begin
if(count5_enable)
begin
if(count5_direction) count5<=count5+1; else count5<=count5-1;
end
if (capture5)
begin
cap5<=count5;
// cap5received<=1;
end
// if (encoder5_reset)
// begin
// count5<=0;
// end
end

always @(negedge encoder6_clk)
begin
if(count6_enable)
begin
if(count6_direction) count6<=count6+1; else count6<=count6-1;
end
if (capture6)
begin
cap6<=count6;
// cap6received<=1;
end
// if (encoder6_reset)
// begin
// count6<=0;
// end
end

 

 

 

 

assign databus[7:0]=(!oe)?dataout[7:0]:8'bzzzzzzzz;
//assign in24=(!sel[2])?ll:24'bzzzzzzzzzzzzzzzzzzzzzzzz;
//assign in24=ll;
assign databus=dataout;
// if oe is low --> read operation.
// if wr is low --> write operation.


endmodule

PID CONTROLER

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:28:15 10/22/2017
// Design Name:
// Module Name: pid-control
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//module pid-control(clock, clocl_en,
// reset, set_point,
// control
// );

//input clock;
//input clocl_en;
//input reset;
//input set_point;
//output reg control;

//module PID // bit width - 1
//output signed [W:0] u_out; // output
//input signed [W:0] e_in; // input
//input clk;
//input reset;
//parameter k1=107; // change these values to suit your system
//parameter k2 = 104;
//parameter k3 = 2;
//reg signed [W:0] u_prev;
//reg signed [W:0] e_prev[1:2];
//assign u_out = u_prev + k1*e_in - k2*e_prev[1] + k3*e_prev[2];
//always @ (posedge clk)
//if (reset == 1) begin
//u_prev <= 0;
//e_prev[1] <= 0;
//e_prev[2] <= 0;
//end
//else begin
//e_prev[2] <= e_prev[1];
//e_prev[1] <= e_in;
//u_prev <= u_out;
//end
//end module;
//

COUNTER 

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:30:01 10/28/2017
// Design Name:
// Module Name: pwm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SimplePWM(clk_in, PWM_out1, PWM_out2);
input clk_in; //clock for counter//input [15:0] x_in; //control value that
//defines pulse width
output reg PWM_out1 = 1; //PWM signal out
output reg PWM_out2 = 1;
reg [3:0] counter = 0;
//reg [7:0] counter2 = 8'b00111111;
reg [2:0] counter2 = 0;
reg out2;
always@ (posedge clk_in )begin
if ( counter <= 4'b0111 )
begin
PWM_out1 <= 1;
counter <= counter+1;
end
else
begin
PWM_out1 <= 0;
counter <= counter+1;
end

if ( counter2 <= 3'b011 )
begin
out2 <= 1;
counter2 <= counter2+1;
end
else
begin
out2 <= 0;
counter2 <= counter2+1;
end
end

always@ (posedge out2 )
begin

PWM_out2 <= out2;

end
/*if (counter2 < 8'b00111111)
begin
PWM_out2 <=1;
counter2 <= counter2+1;
end
if (8'b00111111<=counter2<8'b10111111)
begin
PWM_out2 <=0;
counter2 <= counter2+1;
end
if (counter2 >= 8'b10111111)
begin
PWM_out2 <=1;
counter2 <= counter2+1;
end*/


//else
//begin
//PWM_out2 <=0;
//counter <= counter+1;
//end

endmodule

UART PROJECT

TOP

module top( clk, Rst_n, Rx, Tx, Rxdata);


input clk, Rst_n, Rx;
output Tx;
output [7:0] Rxdata;

 

wire [7:0] Txdata ;
wire Rxdone ;
wire Txdone ;
wire tick ;
wire TxEn ;
wire RxEn ;
wire [3:0] NBits ;
wire [15:0] BaudRate ;

assign RxEn = 1'b1;
assign TxEn = 1'b1;
assign BaudRate = 16'd325;
assign NBits = 4'b1000;


UART_rs232_rx I_RS232RX(
.clk(clk) ,
.Rst_n(Rst_n) ,
.RxEn(RxEn) ,
.Rxdata(Rxdata),
.Rxdone(Rxdone),
.Rx(Rx) ,
.Tick(tick) ,
.NBits(NBits)
);


UART_rs232_tx I_RS232RX(
.clk(clk) ,
.Rst_n(Rst_n) ,
.TxEn(TxEn) ,
.Txdata(Txdata),
.Txdone(Txdone),
.Tx(Tx) ,
.Tick(tick) ,
.NBits(NBits)
);


UART_BaudRate_generator I_BAUDGEN(
.clk(clk) ,
.Rst_n(Rst_n) ,
.Tick(tick) ,
.BaudRate(BaudRate)
);


endmodule

RX_UART

module UART_rs232_rx (clk, Rst_n, RxEn, Rxdata, Rxdone, Rx, Tick, NBits);

input clk, Rst_n, RxEn, Rx, Tick;
input [3:0]NBits;
output Rxdone;
output [7:0]Rxdata;

parameter IDLE = 1'b0, READ = 1'b1;
reg [1:0]State, Next;
reg read_enable = 1'b0;
reg start_bit = 1'b0;
reg Rxdone = 1'b0;
reg [4:0] Bit = 5'b00000;
reg [3:0] counter = 4'b0000;
reg [7:0] Read_data = 8'b00000000;
reg [7:0] Rxdata;

 

///////////////STATE MACHINE//////////////////////

always @(posedge clk or negedge Rst_n)
begin
if (!Rst_n) State <= IDLE;
else State <= Next;
end

//////////////NEXT STEP DICISION/////////////////

always @ (State or Rx or RxEn or Rxdone)
begin
case (State)
IDLE : if(!Rx & RxEn) Next = READ ;
else Next = IDLE ;
READ : if(Rxdone) Next = IDLE ;
else Next = READ ;
default Next = IDLE ;
endcase
end


////////////////Enable Read Or Not//////////////

always @ (State or Rxdone)
begin
case (State)
READ: begin
read_enable <= 1'b1;
end

IDLE: begin
read_enable <= 1'b0
// end
// endcase
// end

////////////////Read the input data/////////////
always @ (posedge Tick)

begin
if (read_enable)
begin
Rxdone <= 1'b0;
counter <= counter+1;

if ((counter == 4'b1000) & (start_bit))
begin
start_bit <= 1'b0;
counter <= 4'b0000;
end

if ((counter == 4'b1111) & (Bit == NBits) & (Rx))
begin
Bit <= 4'b0000;
Rxdone <= 1'b1;
counter <= 4'b0000;
start_bit <= 1'b1;
end
end
end

///////////////output assignment///////////////
endcase
always@(posedge clk)
begin

if (NBits == 4'b1000)
begin
Rxdata[7:0] <= Read_data[7:0];
end

if (NBits == 4'b0111)
begin
Rxdata[7:0] <= {1'b0,Read_data[7:1]};
end

if (NBits == 4'b0110)
begin
Rxdata[7:0] <= {1'b0,1'b0,Read_data[7:2]};

end
endmodule

TX_UART

module UART_rs232_tx (clk ,Rst_n ,TxEn ,Txdata ,Txdone ,Tx ,Tick ,NBits);

input clk, Rst_n, TxEn, Tick;
input [3:0]NBits;
input [7:0]Txdata;

output Tx;
output Txdone;

parameter IDLE = 1'b0, WRITE = 1'b1;
reg State, Next;
reg Txdone = 1'b0;
reg write;
reg Tx;
reg write_enable = 1'b0;
reg start_bit = 1'b1;
reg stop_bit = 1'b0;
reg [4:0] Bit = 5'b00000;
reg [3:0] counter = 4'b0000;
reg [7:0] in_data = 8'b00000000;
reg [7:0] R_edge;
reg D_edge;

 

///////////////STATE MACHINE//////////////////////

always @(posedge clk or negedge Rst_n)
begin
if (!Rst_n) State <= IDLE;
else State <= Next;
end

//////////////NEXT STEP DICISION/////////////////

always @ (State or D_edge or Txdone)
begin
case (State)
IDLE : if(D_edge) Next = write ;
else Next = IDLE ;
write : if(Txdone) Next = IDLE ;
else Next = write ;
default Next = IDLE ;
endcase
end


////////////////Enable write Or Not//////////////

always @ (State)
begin
case (State)
write: begin
write_enable <= 1'b1;
end

IDLE: begin
write_enable <= 1'b0
// end
// end
// end

/////////write the data out on Tx pin/////////////
always@(posedge Tick)

begin
if (!write_enable)
begin
Txdone = 1'b0;
start_bit <= 1'b1;
stop_bit <= 1'b0;
end

if (write_enable)
begin
counter <= counter+1;
end

if (start_bit & !stop_bit)
begin
Tx <= 1'b0;
in_data <= Txdata;
end

if((counter == 4'b1111) & (start_bit))
begin
start_bit <= 1'b0;
in_data <= {1'b0,in_data[7:1]};
Tx <= in_data[0];
end

if((counter == 4'b1111) & (start_bit) & (Bit < NBits-1))
begin
in_data <= {1'b0,in_data[7:1]};
Tx <= in_data[0];
start_bit <= 1'b0;
counter <= 4'b0000;
end

if((counter == 4'b1111) & (Bit == NBits-1) & (!stop_bit))
begin
Tx <= 1'b1;
counter <= 4'b0000;
stop_bit <= 1'b1;
end

if((counter == 4'b1111) & (Bit == NBits-1) & (stop_bit))
begin
Bit <= 4'b0000;
Txdone <= 1'b1;
counter <= 4'b0000;
// start_bit <= 1'b1;
end

end
end

///////////////input enable detect///////////////
endcase
always @(posedge clk or negedge Rst_n)
begin

if (!Rst_n)
begin
R_edge <= 2'b00;
end

else
begin
R_edge <= {R_edge[0], TxEn};
end

end

assign D_edge = !R_edge[1] & R_edge[0];


//endmodule

BAUD_RATE_GEN

module UART_BaudRate_generator( clk, Rst_n, Tick, BaudRate );

input clk, Rst_n;
input [15:0] BaudRate;
output Tick;

reg [15:0] baudRateReg;

always @(posedge clk or negedge Rst_n)
if (!Rst_n) baudRateReg <= 16'b1;
else if (Tick) baudRateReg <= 16'b1;
else baudRateReg <= baudRateReg + 1'b1;

assign Tick = (baudRateReg == BaudRate);

endmodule

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