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dimpy
Adventurer
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Registered: ‎06-05-2020

ADRV9361-Z7035 LVDS to LVTTL conversion

Hello,

I am working on ADRV9361-z7035.We have to read and write data from the external device for that we need to convert signals from LVDS to LVTTL and LVTTL to LVDS. We are using two banks(bank 12 and 13). Kindly guide me how to do it in Vivado and where to start?

Waiting for your response.

Thank you.

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7 Replies
dimpy
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Registered: ‎06-05-2020

Hello 

Kindly reply on my previous question.

Thank you.

 

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Registered: ‎01-22-2015

@dimpy 

I see that the ADRV9361-Z7035 uses the Xilinx XC7Z035-L2 FBG676I.  From UG865 we find that banks 12 and 13 of the Z7035 are PL-side HR banks. 

If you power banks 12 and 13 of the Z7035 with VCCO=2.5V then pins on these banks can be configured to send or receive either LVDS_25 or LVCMOS25 as shown in Table 1-55 of UG471(v1.10).  That is, once the FPGA pins are configured properly, the conversion from LVDS_25 or LVCMOS25 to the internal logic used by the FPGA is done automatically. 

I know that you specified LVDS and LVTTL.  You should check the datasheet, DS191, of the Z7035 for specifications of LVDS_25 and LVCMOS25 to see if they are compatible with your specifications for LVDS and LVTTL.

Cheers,
Mark

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dimpy
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Registered: ‎06-05-2020

Hello markg@prosensing.com 

Thank you for your reply.

I am new FPGA. And yes we are using bank 12 and bank 13 which are PL-side HR banks. From the ADRV9361-z7035 both are using LVDS_25 conversion and it goes into the bank 35. We have to route the signal from Bank 35 to bank 12 or 13 to connect external device for that we want to do LVDS to LVTTL conversion. 

Kindly guide me step by step how should i do program in Vivado for this application? 

Waiting for your response.

Thank you.

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Registered: ‎01-22-2015

@dimpy 

From the ADRV9361-z7035 both are using LVDS_25 conversion and it goes into the bank 35. We have to route the signal from Bank 35 to bank 12 or 13 to connect external device for that we want to do LVDS to LVTTL conversion. 

I see that bank 35 is an HP bank.  If a differential signal is going into bank-35 then you should use the IOSTANDARD called LVDS (and not LVDS_25).  Please refer to page-91 of UG471(v1.10) for differences between LVDS and LVDS_25.

After the signal enter the FPGA from the bank-35 pin, it will automatically be converted to a single-end signal.  That is, all signals inside the FPGA are single-end.

If you use VCCO=3.3V to power bank-12 and bank-13, then pins/ports of these banks can use the LVTTL IOSTANDARD to output the signal (again, see UG471).

In the HDL (eg. VHDL or Verilog) that you write for the PL-side of the Z7035, you can simply connect the signal coming from a port/pin in bank-35 to a port/pin in bank-12 or bank-13.  Once the signal reaches a pin/port that you have specified to use the LVTTL IOSTANDARD then the signal will automatically be converted to LVTTL.

 

 

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dimpy
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Registered: ‎06-05-2020

Hello markg@prosensing.com 

Thank you for your answer.

I have another questions regrading it, kindly find the below questions.

As you said In the HDL (eg. VHDL or Verilog) that you write for the PL-side of the Z7035, you can simply connect the signal coming from a port/pin in bank-35 to a port/pin in bank-12 or bank-13.  Once the signal reaches a pin/port that you have specified to use the LVTTL IOSTANDARD then the signal will automatically be converted to LVTTL.

1). We have 6pair of pins are as transmitter and 6pair of pins are as receiver. Could you show me some example code which is relevant with my requirement? 

2). I have to use IBUFDS for converting the input LVDS to LVTTL and OBUFDS for output signal and clock ?

3). I need to write constraints for connect the signal coming from a port/pin in the bank-35 to a port/pin in the bank 12 or bank 13?

4). I need to create block diagram for it or when i write the code for same it will create the block diagram automatically?

Waiting for your response.

Thank you.

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dimpy
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Registered: ‎06-05-2020

Hello markg@prosensing.com @barriet 

Kindly give an answer of my questions.

I am waiting for your response.

Thank you.

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sabankocal
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Registered: ‎08-02-2019

Hi @dimpy ,

I got your private message in the Community Forums and I'll try my best to help you.

You say: "I'm new in FPGA", then we can start from some basics:

To implement your task, first we need to understand what is the difference between LVTTL, LVDS, LVCMOS...

Mainly we can say, we can handle FPGA pins as 2 diffrent types:

  1. Differential pins : LVDS, LVDS_25... uses 2 pins(negative and positive), but if you need you can use same pins as single ended also. 
  2. Single Ended pins: LVCMOS is well known type of signle ended. You can select one of LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25, LVCMOS33 according to your design. Suffix 33 referes 3.3V, 18 referes 1.8V. Why it is so important? Because in a Bank of FPGA you must always use same Voltage level. If we talk about Bank12, we need to select proper Voltage level according to our needs. If our incoming signal or outgoing signal needs 2.5V we need to use LVCMOS25 or LVDS_25 according to single ended or differential.
  3. We need to understand firstly what is the difference between LVCMOS and LVTTL. There is no big difference between them. LVCMOS is more flexible about voltage level as I mentioned before, on the other hand LVTTL refers hihger voltage levels as mentioned here. Fact is that: your design needs which of them?

About FPGA implementations only difference that changes your implementation is "Single Ended" or "Differential", other voltage level design selections are only related with our constraints file, not related with FPGA implementations(Verilog/VHDL or block design).  

 

3.3V Single Ended signal example:
set_property	PACKAGE_PIN	H13	[get_ports	Incoming_Signal_A]					
set_property	IOSTANDARD	LVCMOS33	[get_ports	Incoming_Signal_A]

2.5V Differential signal example:
set_property DIFF_TERM	TRUE	[get_ports	Incoming_Signal_B]					
set_property -dict {PACKAGE_PIN G1	IOSTANDARD	LVDS_25	DIFF_TERM	1}	[get_ports	Incoming_Signal_B]

 

Now we can talk about your questions:


1). We have 6pair of pins are as transmitter and 6pair of pins are as receiver. Could you show me some example code which is relevant with my requirement? 

2). I have to use IBUFDS for converting the input LVDS to LVTTL and OBUFDS for output signal and clock ?

Sample Code, converts LVDS to Single Ended as input signal and Single Ended to LVDS as output signal.

i_buffer : IBUFDS
port map (
O => single_input,
I => diff_input_p,
IB => diff_input_n
);

OBUFDS #(
.IOSTANDARD("LVDS_25") // Specify the output I/O standard
) OBUFDS_inst (
.O(ServoDataToSOCp), // Diff_p output (connect directly to top-level port) (p type differential o/p)
.OB(ServoDataToSOCn), // Diff_n output (connect directly to top-level port) (n type differential o/p)
.I(Servo_Data) // Buffer input (this is the single ended standard)
);

3). I need to write constraints for connect the signal coming from a port/pin in the bank-35 to a port/pin in the bank 12 or bank 13?

incoming and outgoing signals are independed from each other. First you need to handle incoming signals(find which pin you need to define in your constraints file, choose proper voltage level, convert it to single ended if it is differential.

After all you have  related signal in FPGA design, you can use it in your design and after all you can send it as outgoing signal(directly single ended or by converting it to differential again)

4). I need to create block diagram for it or when i write the code for same it will create the block diagram automatically?

In Vivado we have two options:

Working with only scripts or working with block designs. If you are new in FPGA, working with block design is better for you. you can simply find a base Vivado block design with your chip(becasue there are a lot of chip specific settings, speed etc., you need to be carefull about them)

than you can add your Vivado/VHDL files into that basic design and by right clicking your newly created file-->"Add Module to Block design" you can add it into your block design. You can find my previous post here,.it shows block design view.

You can find also sample vivado implementation about lvds to single ended here. it is already selected as solution.

 Saban

 

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