About A7 FPGA's ff reset

[rggber]

Hi all:

   For A7 fpga's ff(also include those in IOB),I submit 2 questions:

How to specify the value of ffs. These are 2 kinds of "reg"s in my verilog based project:

1. "reg"s need to have a preset value after fpga's configuration but no require for reset signal. Usually these are registers for pipline.

2. "reg"s need both. 

To 1. I am going to do as:

reg[7:0] reg_mt = 8'b0000_0000;

To 2. I am going to do as:

reg[7:0] reg_mt = 8'b0000_0000;

always@(posedge sys_clk)

begin

    if(sys_rst) reg_mt <= 8'b0000_0000;

    else

       ...

end

are they the correct way of using ffs in A7 fpga?

Is it recommended to use sync reset to ffs with high active? Usually the reset signal is provided by fpga's pin connect to other chips or a press key, they are async to fpga. Is it necessary to synchronize the external reset signal by sys_clk and other clk domains?

[jmcclusk]

Active high synchronous reset is the recommended flavor.   And if your reset comes from an external source, it MUST be synthronized into the destination clock domain FIRST.     Never apply a reset if it hasn't been synchronized.

[drjohnsmith]

the second will infer a FF,

the first a constant, as it has no clock dependency.

the tools are timing driven,

 if you use asynchronous, the tools can not help you, you are on your own for timing.

    The simple answer is to have a registered reset internal,  in a shift register,

           the registers of which are asynchronously set by reset and at power up also set.

then after a set number of clocks after the external reset is released, 

this is the classic paper by Ken Chapman

https://www.xilinx.com/support/documentation/white_papers/wp272.pdf