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Explorer
Explorer
952 Views
Registered: ‎01-04-2013

About interrupt invector of sdk

Hello everyone

I have a vivado(2015.4) project like this

中断连接.png

 

the block design is submodule of my verilog top-level

中断连接2.png

I connect my signals to bd in top-level verilog source

中断连接3.png

 

but when I export my design to sdk,I only find interrrpt vector (number is 61) in the head file "xparameters.h",the interrupt wIntr_flaw and wIntr_frame has no interrupt vector

 

中断连接4.png

 

Thanks for your help

 

Best wishes.

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3 Replies
Adventurer
Adventurer
930 Views
Registered: ‎11-13-2017

Re: About interrupt invector of sdk

Hi,

 

Are the port properties for intr_frame/intr_flaw in the block-design assigned as interrupt types?

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929 Views
Registered: ‎06-21-2017

Re: About interrupt invector of sdk

Do your external interrupt signals have Interrupt attributes attached to them.  Vivado isn't smart enough to know that if you attach a signal to the interrupt input of a Zynq, you want the signal to act as an interrupt.  It's a long and winding thread, but check this https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/INT-ID/m-p/800241#M16657

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Explorer
Explorer
900 Views
Registered: ‎01-04-2013

Re: About interrupt invector of sdk

Thanks for your replying

I can infer the signal to interrupt type when I package my fabric to a user ip which is added to the block design,but now I want to make my all verilog module as sub-module of the top-level ,so I don't know how to make the signals as a interrupt type

 

Best Wishes

 

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