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rkfournier
Adventurer
Adventurer
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Registered: ‎05-09-2018

Artix-7 DIFF_TERM Tolerance Specification

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Where can I find the tolerance specification for the 100 ohm differential termination on an LVDS_25 input? I can only enable or disable the termination. The datasheet has the Rin_term specifications that I attached, but the SelectIO Resources UG471 states these are only applicable to the HP banks The Artix-7 has HR banks.

Rin_term.jpg
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drjohnsmith
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Teacher
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Registered: ‎07-09-2009

Confused as to why you want to know the impedance tolerance,

       Im not certain myself

   but remember it not a real resistance, but a current mirror circuit in the FPGA, so its self regulating to some degree.

 

People that want to know the details of IO, tend to be looking at simulation

   I'm afraid, if you want to know any more , then Xilinx , like most other silicon vendors, provide IBIS for simulation,

   

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drjohnsmith
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Teacher
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Registered: ‎07-09-2009

100 Ohms is what you need to know,

    thats what you design your tracks for , thats what the Tx expects.

If your not using the IO as digital, or you want more details on how the IO voltage and current works,

    then look at page 21, which indicates  you need to do the IBIS simulation, 

https://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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rkfournier
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Registered: ‎05-09-2018

Sorry if my request was not clear. I understand the termination is 100 ohms.  Die to die, wafer to wafer is this 100 ohms +/-1%, +/-5% or some other value? Please note that I do not have IBIS simulation capability.

We are using the I/O at 2.5V on both ends of a 500 megabit/s SDR serial link based on the OSERDESE2 and ISERDESE2 resources. Our signal path is approximately 750mm in length between two boards. The transmit end is using a Spartan-7 while the receive end is using an Artix-7. There are two FPC connectors and a shielded, 515mm FFC cable connecting the two boards. All PCB traces are designed as differential pairs with a characteristic differential impedance of 100 ohms. The FFC cable is also designed for a differential impedance of 100 ohms.

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drjohnsmith
Teacher
Teacher
451 Views
Registered: ‎07-09-2009

Confused as to why you want to know the impedance tolerance,

       Im not certain myself

   but remember it not a real resistance, but a current mirror circuit in the FPGA, so its self regulating to some degree.

 

People that want to know the details of IO, tend to be looking at simulation

   I'm afraid, if you want to know any more , then Xilinx , like most other silicon vendors, provide IBIS for simulation,

   

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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