08-27-2015 06:45 AM
I have a couple specific questions about the Artix 7 IOBs. I cannot seem to find the answers to these anywhere in the provided Xilinx documentation. If you know of where these answer are in the documentation, I would love to know. I appreciate the help.
1. How is the Hi-Z implemented, hardware wise, in the IOB? Is it implemented with a resistor or FET?
2. Can I directly drive I2C lines with the FPGA output directly (they require open-drain interfaces)?
3. What resistance is used when the PULLUP constraint is used?
4. What resistance is used when the PULLDOWN constraint is used?
08-27-2015 07:16 AM
2. yes (open drain is tristate control is used as the data -- tristate is '1', and not tristate with a zero as input to the IOB is '0')
3. In the data sheet
4. In the data sheet
Be sure the Vcco of the IO bank used for I2C is equal to the I2C component's Vdd.
08-27-2015 09:22 AM - edited 08-27-2015 09:28 AM
Those I/O pullups tend to be in the range of 50K Ohms to 100K Ohms. That kind of resistance is too high to provide the pullup for an I2C interface. I2C uses a pullup resistor to privide the rising edge on signals. Normally you want 1K Ohms or less for that.
Put resistors on your board.
You can then infer your Tri-state I/O like this.
if (whatever) then
SDA <= '0';
SDA <= 'Z';
Also, I am not sure about what Austin says about Vcco. I2C was conceived to allow chips of different I/O standards to communicate. The idea is that the on-board pullup resistor establishes your logic 1 voltage. Chips on the bus only pull down to ground. As long as the FPGA pin can be safely pulled up the logic 1 level you should be ok.
08-27-2015 09:10 PM
08-27-2015 09:09 PM
09-01-2015 01:48 PM