Artix 7 Input Pin Resistances

[wigao0822]

Where do I find input pin resistances for Artix 7 device? I looked at DS181 datasheet and wasn't able to find what I am looking for. On some Xilinx forums they suggested to use Vcco/Max leakage current to find input resistance. 3.3V/15uA=220K Ohms, which is significantly small for an input resistance. My concern is the following

-I have a FPGA output that connects to an external circuit that has a some resistance at the mega ohm magnitude. 

- The external circuit is then connected to a FPGA input. 

-Both FPGA output and inputs are configured to a LVCMOS33 io standard.

- I have to find the input pin resistance, such that the voltage drop caused by external circuit will not cause the voltage level to fall below LVCMOS33's voltage threshhold.

-LVCMOS Vout is 3.3V, V thresh hold is 2.0V, so the equation is 1.3V >3.3V (R external circuit/(R external circuit + R input pin resistance))

What is R input pin resistance. 

[archangel-lightworks]

Probably there is no such thing as 'resistance' for the simple reason they are not resistors.

If you generate an IBIS model of your FPGA, specifying the standard for the pins you are interested in, you can get the V-I points, if that helps.

The problem with leakage currents is they are not design parameters (i.e. nobody cares too much about them) and they vary with PVT, so the best number you may get is a worst-case figure. If you want one, mine is 10 uA.

If you have high impedances so the small leakage currents cause unacceptable voltage drops, what I would do is simply to buffer that thing. A simple logic gate could be all you need.

[archangel-lightworks]

Just an afterthought...

If your FPGA pin is an output, you don't need to worry about the output voltage going out of specs, unless you need that signal for another digital input.

If your FPGA is an input and you have that megaohm pullup or pulldown you can still buffer it with a logic gate and it's gone

[wigao0822]

How would I use the IBIS model in my scenario. I am looking at the .ibs file and there are operating conditions to calculate for pull up and pull down, gnd, power, rising time, falling time. I don't see something for input resistances though. I do see something called R ref and its value is 1M Ohm, is that what I am looking for?

[archangel-lightworks]

I think the IBIS models are too complex for what you want. They are used in AC simulations of signal integrity, while what you want is a static leakage current. 

By the way, what about getting the board, using a spare i/o pin, having a wire to a breadboard, sticking a megaohm resistor to VCC or GND and measuring it? Just remember it depends on your i/o standard and if you have enabled or not any internal pull-up

[wigao0822]

I do need that signal, that same signal is going right back into an FPGA input. Buffer it with a logic gate? Can you elaborate a little on that. A logic gate still means it needs to see the proper digital value, which is only after the input signal is above 2V voltage threshold for LVCMOS33, isn't that so? Like if it fell to 1.2V, it will be read as a 0, going into the buffer?

[wigao0822]

I might have to do that, I was just confused as to why what seems to be very important spec, isn't readily available in the datasheets.

[drjohnsmith]

A good logical question , but one thats not needed in the digital world.

Reason, Digital outputs are specified as being able to source / sink a certain current at a certina voltage.

Digital inputs are speced to need a certain voltage for a 1/0 at a certina source / sink current.

All yo uneed to do is ensure your dirver can provide sufficient current at Voh and Vol, to drive the Vinh and Vinl of the receive chips.

Rule of thumb is one logic output can drive 10 logic inputs !

Yes its a very old rule , and many exceptions, as I'm certain others will mention,

So, go to the data sheets,

find the Voh and Vol, and at what currents they are at.

   go to the receivers, and find the Vin High and Low, and what currents they need at that .

            you shoudl find you have plenty of current, so it will work.

This from an old Spartan 3, I just happen to have the data sheet for on the phone !!

[archangel-lightworks]

Probably because those currents vary in orders of magnitude with temperature and having high impedances straight away to an FPGA (or any digital i/o) is not the usual thing.

Another potential problem with high resistances (over 10 meg) is that PCB resistance begins to be noticeable (100s of megs) and will vary from PCB batch to batch. Even worse is the effect of dust, grease and other stuff that goes to the PCB over time. 

[drjohnsmith]

can you draw us a little picture please.

I have this as

FPGA -> ------------------------+---------------------------- -> FPAG

out                                  |meg resistance |                    in

so the resistance is just on the track, either pulle dup or down to some volts.

as such, I'd have thought all the current will flow through the track, its just a FPAG to FPGA connectoin, which is a no brianer.

The mega ohm resistance has "zero" affect on the current flow or the voltage.

[lowearthorbit]

all,

Most pcb assembly today uses water soluble fluxes, so I have have seen board leaage as bad as 100K ohms,

A really dirty rinse can result in even lower resistance due to salts in the water!

So, the leakage of the IC design of the IOB is perhaps at least one order of magnitude greater than a good clean pcb, and can be three to six orders of magnitude better (basically, you cannot measure it).

l.e.o.

[wigao0822]

I think I agree with you that all the current will flow through, however isn't there a voltage drop on [meg resistance]? You said earlier that the FPGA drives current source on outputs, and checks for voltage on input. 

[lowearthorbit]

Leakage in in parellel,

Not in series.  So, the voltage at the pin is unaffected by the leakage current when driven by the appropriate output stand.

l.e.o.

[drjohnsmith]

can you draw us a picture please,

stiil uncertain as to where this resistor is in relation to the fpga out and in pins.

Also un certina as to what your trying to do ,

    the FPGA logic input can not meassure voltage, it only cares is th evoltag eis above or below a certain level,

( Yes there are on some FPGAs ADC's that can meassure , but again its unclear as to your circuit )

[wigao0822]

Sorry about that. 

Your picture was accurate. 

I understand that the input only sees whether or not it is higher than voltage thresh hold to decide 1 or 0. Which is why I am concerned about voltage drop on the [meg resistor]. 

[drjohnsmith · Accepted solution]

so the 1 M resitor is going to ground,

 Assuming you have at most a 3v3 output from the FPGA,

thats 3v3 across 1 Mohm current 'lost' due to the reistor.

whihc is less than 4 micro Amp.

    Depending on the drive chosen for the FPGA,

         the default output current capabiltiy of the pin is around 6 mA. and that can drive 10 other FPGAs as a rule of thumb, ( look in data sheets for detail current in and out )

so if your driving one fpga input and the 1 M resitor yo need a minumim of 6 mA/10 + 4 micro amps,

At DC, the resitor has zero real effect on the output voltage or current of the FPGA.