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Visitor
Visitor
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Registered: ‎01-09-2020

Artix-7 applying power to I/O pins

For the Artix7 XQ7A200T-2RB676I, are there any concerns with applying voltage to the I/O pins when the FPGA is not powered? Currently, we have a power-on setup where multiple discretes at a voltage of about 2.8V are being applied to the I/O pins of the FPGA before the FPGA is powered on. A few seconds afterwards, the FPGA is powered on. The discretes go through a resistor network which limits the current to a maximum of .325mA. Is there risk of damage to the FPGA or is there some sort of input protection of the I/O pins when the FPGA is not powered?

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-06-2018

Hi @darlm ,

Unpowered pins still have clamp diodes present that will be forward biased when a pin voltage is applied.

There are two aspects of the device specifications that must be considered when determining if a device could be damaged. For more information refer this AR#34347 .

Hope this helps.

Regards,
Deepak D N
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Visitor
Visitor
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Registered: ‎01-09-2020

We are not using a battery on our board, so Vccaux and VCC are both 0V, when the I/O voltages are applied to the I/O pins. Therefore, in order to not violate the (Vcco - Vccaux) spec, we want to keep Vcco at 2.625V max.

So, does this mean that the maximum Vin that can be applied to an unpowered bank in our case, assuming a .43 diode drop would be approximately 2.625V+.43V = 3.055V, to prevent risk of damage to the device?

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Community Manager
Community Manager
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Registered: ‎08-08-2007

Hi @darlm 

 

When your bank is unpowered the Vcco = 0V, therefore the Vin which is recommended to be Vcco + 0.2V = 0 + 0.2V = 0.2V

 

Therefore when the bank is unpowered the Vin should be below 0.2V. 

The Absolute Max rating for Vin = Vcco + 0.55V = 0 + 0.55V = 0.55V, when the bank is unpowered that absolute max Vin should be 0.55V.

 

Regards,

Sandy

Thanks,
Sandy

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Community Manager
Community Manager
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Registered: ‎08-08-2007

Hi @darlm 

I will try to write a more complete answer here. 

As I said when the bank is unpowered you cannot use the expected max of 2.625V in the Vin equation. Theoretically the Vcco is 0 for an unpowered bank and the Vin becomes 0.2V.

Xilinx in general does not recommend driving I/Os when Vcco in unpowered. When the bank is unpowered and IOs are driven the clamp diode turns on. 

As @ddn pointed to  AR : https://www.xilinx.com/support/answers/37347.html

Where you need to consider the current through the clamp diode, Iin has a recommend limit in the datasheet of 10mA per diode with a total of 200mA per bank.

For 7 Series there is the TVCCO2VCCAUX specification that @ddn mentioned. The concern is that powering the IOs can reverse biasing the Vcco before the Vccaux and bring the TVCCO2VCCAUX specification in to be consider.

We also have a specific AR addressing the reverse biasing of the Vcco and how to limit the current to meet the TVCCO2VCCAUX specification.

https://www.xilinx.com/support/answers/45985.html

 

If you ensure that all specifications are met there should be no issues with long term reliability.

 

Sandy

Thanks,
Sandy

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