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Observer
Observer
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Registered: ‎03-14-2019

Artix 7 pin placement guidelines

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what guidelines should be followed to get optimal pin placement? I need some help in following topics:

 

FPGA bank selection:

My chosen Artix7 device only have HR banks and same pin count in every bank, so as I understand there is no difference what FPGA bank I will chose?

 

Clock input placement:

MRCC or SRCC pins? In general MRCC would be better choice for this purpose?

 

Clock output pin placement:

I think there is no special pins for clock output, so any general purpose pin can be used?

 

I/O placement:

How do I chose pins in FPGA bank for I/O to get optimal timing or SSN? I have source synchronous input interface and source synchronous output interface. Should i place interface pins next to each other? Is there any restrictions where pins with differenctial standarts can be placed, besides folowing P/N pairs?

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Artix 7 pin placement guidelines

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a lot of hand holding there

start with SSN
https://www.xilinx.com/support/answers/31905.html


A clock for a dac is not as much of a worry as a ADC,
the noise introduced by the clock jitter is spread out over the nyquest zones as opposed to all folding back into the first nyquest zone.

Read up on
https://www.analog.com/media/en/reference-design-documentation/design-notes/dn1013f.pdf

http://www.ti.com/lit/an/slaa566/slaa566.pdf


re design flow,
this is what you need to read up on
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug949-vivado-design-methodology.pdf


Re your last comment,
experiment see what happens when you change stuff.


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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Artix 7 pin placement guidelines

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Easy answer, all above look about right,

Optimal timing you ask, let the tools do that for you,

Clock out ? What clock out do you want to do ?
If its for a ADC / DAC , at any sort of frequency , dont do it .

SSN,
the more stuff you have changing at once, on any one bank the more noise it will make, The more current they output drive, the more noise, The faster the slew rate, the more noise.

If you only have a few clocks coming into the FPGA, then the MRCC cover all quadrants of the chip, and are easier to use.

Ensure your clock comes in to a MMCM , and then use the clocks from that inside the FPGA.



Bottom line, if your un certain, do a test fpga design, see what the reports are BEFORE you lay your board out.


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Xilinx Employee
Xilinx Employee
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Registered: ‎06-13-2018

Re: Artix 7 pin placement guidelines

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Hi @vytbuit :

Adding to @drjohnsmith comments, if you are using MMCM, PLL,BUFG, BUFH etc. ie global clocking resources, then the MRCC and SRCC both can be used except the BUFMR (multi clock region buffer) which can be driven by MRCC only. 

Refer https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf , page 24 for detailed information.

SrrccMrccPins.JPG

If you don't need BUFMR, then I believe its better to use the SRCC pins first.

 

Thanks,

Priyanka

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Observer
Observer
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Registered: ‎03-14-2019

Re: Artix 7 pin placement guidelines

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Thank you @drjohnsmith for your answer. Can I kindly ask you to be more specific with your answers, because I know some basic principles but I dont have much real design experience with Xilinx FPGA and Xilinx tools. 

 

Optimal timing you ask, let the tools do that for you,

How do I do that? Compile design without pins assigned and see what pin location tool suggests? 

Clock out ? What clock out do you want to do ?
If its for a ADC / DAC , at any sort of frequency , dont do it .

Yes, for DAC. Can you explain why and then how should I do it? Use system synchronous design approach instead of source synchronous? I know that clock from FPGA resources have larger jitter which can cause some performace degradation for DAC compared to external clock generating IC but I dont have much real design experience to compare these two solutions.  

SSN,
the more stuff you have changing at once, on any one bank the more noise it will make, The more current they output drive, the more noise, The faster the slew rate, the more noise.

How do I check them? 

Bottom line, if your un certain, do a test fpga design, see what the reports are BEFORE you lay your board out.

Yes, I am allready doing test design but I would like to know what I am doing and what Vivado are saying to me. 

thank you @drjohnsmith 

 

 

 

 

 

 

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Artix 7 pin placement guidelines

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a lot of hand holding there

start with SSN
https://www.xilinx.com/support/answers/31905.html


A clock for a dac is not as much of a worry as a ADC,
the noise introduced by the clock jitter is spread out over the nyquest zones as opposed to all folding back into the first nyquest zone.

Read up on
https://www.analog.com/media/en/reference-design-documentation/design-notes/dn1013f.pdf

http://www.ti.com/lit/an/slaa566/slaa566.pdf


re design flow,
this is what you need to read up on
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug949-vivado-design-methodology.pdf


Re your last comment,
experiment see what happens when you change stuff.


<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post