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vnesterov
Participant
Participant
6,445 Views
Registered: ‎12-10-2015

Bad Z-state

Hi!

I am using z-7020 and I need changing voltage supply level on FPGA Bank 13 to get pulses with different amplitude. And also I need to turn them to high-impedance state sometime.

I have found that when bank voltage in range from ~1.5V to ~2.2V I can see the same voltage level on output pin in Z-state.

I added OBUFT to check it: OBUFT OBUFT_inst (.O(bank13_pin), .I(1'b1), .T(1'b1));
As result:
1) when Bank supply voltage from 0 to 1.5V - pin in Z-state;
2) when Bank supply voltage higher than 1.5V the pin turn to low level and beco to grow, when supply voltage near 2.2V the pin has the same output value (near 2.2V);
3) when Bank supply voltage higher than 2.2V - pin in Z-state.

Any suggestions?

 

Thanks

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3 Replies
austin
Scholar
Scholar
6,393 Views
Registered: ‎02-27-2008

v,

 

IO have weak pullups or pulldowns if you specify them. If not specified, there is still leakage (+/- 10 uA max) so there is likly some voltage at the pin.  To verify the Z state, measure voltage with a 1k ohm load to gound, and then to Vcco.  It should measure 0.0v and Vcco, respectively,

Austin Lesea
Principal Engineer
Xilinx San Jose
vnesterov
Participant
Participant
4,862 Views
Registered: ‎12-10-2015

Austin,

 

Thanks for answer, I tried to follow your recommendation.
I set the pins of BANK 13 as constant output in Z-state. One of them I loaded to ground and one to Vcco (connected to Vcco_35 of other bank) through 1k ohm resistors.
I got the next situation:

 

z_all.gif

 

Here Vcco_13 from external power supply and Vcco_35 from on-board power supply.
And other picture:

 

z_no_load.gif

 

In my results, when Vcco_13 in range from 1.6V to 2.2V, the pins of that bank which should be in Z-state are not in correct Z-state. What am I doing wrong?

 

Thank you

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vnesterov
Participant
Participant
4,077 Views
Registered: ‎12-10-2015

I didn't understand what exactly was a reason of problem, but I found how to resolve it.

 

My mistake was that I set property IOSTANDARD LVCMOS18 for that bank and supply it by voltage up to 3.3V.

When I changed it to IOSTANDARD LVCMOS33 the effect almost disappeared.

 

 

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