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Visitor gilessj
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Registered: ‎10-15-2019

Bank 14 reconfiguration of VCCO, Artix 7

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Hello,

This is my first post, please be gentle ;)
I am in the process of designing a FMC carrier card, with multiple LPC connectors and a single HPC connector. As such, I am very close to maxing out the I/O available on my target (XC7A200T-1156FCBGA, Artix 7).

My issue comes down to bank 14. I am a bit puzzled by why Bank 0 (which I would consider to be the housekeeping/configuration bank) does not contain a full QSPI interface and at least a I2C interface, but I'm not an IC designer. In my case, I am using bank 14 for I2C (which handles IPMI for the FMCs), for the quad SPI, for FCS (the flash chip select) and EMCCLK. As such, I need to have banks 0 & 14 up before I can configure the VADJ voltages for the FMCs.

The problem, then, is that bank 14 is already at a predefined voltage; since I am fully utilizing the I/O on bank 14, I now have to level shift everything interfacing with the configured I/O standard for the FMC (in this case, I am interfacing only HB(n) pins of the FMC with bank 14, thus I can use VIO_B_M2C to define the other side of a level shifter). This is not too much of a problem if the use case is only single-ended signals, but there may very well be a demand for differential.

In my mind, if I could reconfigure the bank 14 VCCO after configuration has completed, I could avoid all the level-shifting nonsense and have all the lovely termination and configuration goodies available in the FPGA.

I did find the following thread that seems to indicate this is a bit easier in the 7-series (due to POR not monitoring VCCO voltages after config): Change bank voltage from 3.3V to 2.5V after power on 

I have no doubt that the information I desire is in the docs. I have read through thousands of pages, and my eyes are getting crossed at this point. A little help along the way would be greatly appreciated.

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353 Views
Registered: ‎01-22-2015

Re: Bank 14 reconfiguration of VCCO, Artix 7

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-a very interesting problem!

As noted by Austin in the post you referenced, it is not just a matter of powering down a bank and then powering it up with a new VCCO.  You also need to configure the FPGA with a bitstream that was generated using constraints appropriate for the new VCCO (eg. LVCMOS33 instead of LVCMOS15). 

Perhaps you need a separate processor (eg. microcontroller) on the board that can access all the FPGA bitstreams that might be needed.  This processor boots first, polls the FMC to find the needed VCCO_14, sets VCCO_14 to the needed value and powers-up the FPGA, grabs the appropriate bitstream, and uses this bitstream to configure the FPGA (see Fig 2-2 Slave Serial in UG470).

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398 Views
Registered: ‎01-22-2015

Re: Bank 14 reconfiguration of VCCO, Artix 7

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@gilessj 

Welcome to the Xilinx Forum!   No worries about “first post” – you’re doing great!

Table 2-6 of UG470 says (as you do) that bank 0 and bank 14 of the Artix-7 are needed for a SPIx4 configuration interface.  

Table 2-6 of UG470 (as well as Artix-7 datasheet, DS181) also show that VCCO for banks 0 and 14 can be anything from 1.5V to 3.3V.  For almost any voltage in the range 1.5V-3.3V, you can (I think) purchase SPIx4 flash.

So, what is restricting you from setting VCCO_14 to the level you need for the FMC interface?   What do you want VCCO_14 to be?

Cheers,
Mark

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Visitor gilessj
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Registered: ‎10-15-2019

Re: Bank 14 reconfiguration of VCCO, Artix 7

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Hi Mark!

Either you are a very fast reader, or you have the docs memorized! Thank you for your insight.

The problem I'm facing is that according to the VITA57 specs, VADJ(FMC) should be on the same rail as VCCO for the FPGA bank it is interfacing with.

I need to have bank 14 up to handle the I2C interface for the IPMI, which will instruct my rails as to what voltage they should meet for FMC VADJ.

In order to configure bank 14 so that it would match the VCCO requested by the FMC, I would have to predefine that by jumpers (or equivalent), which would violate the programmatic handling of VADJ/VCCO levels per VITA57.

To answer the following question more directly:

"So, what is restricting you from setting VCCO_14 to the level you need for the FMC interface?   What do you want VCCO_14 to be?"

The restriction is that until VCCO_14 is up at some predefined voltage, I cannot poll the FMC to find its required voltage (nor can I configure the FPGA via QSPI). Until VCCO_14 is up, I have no idea what the required voltage will be.

Thanks again.

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354 Views
Registered: ‎01-22-2015

Re: Bank 14 reconfiguration of VCCO, Artix 7

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-a very interesting problem!

As noted by Austin in the post you referenced, it is not just a matter of powering down a bank and then powering it up with a new VCCO.  You also need to configure the FPGA with a bitstream that was generated using constraints appropriate for the new VCCO (eg. LVCMOS33 instead of LVCMOS15). 

Perhaps you need a separate processor (eg. microcontroller) on the board that can access all the FPGA bitstreams that might be needed.  This processor boots first, polls the FMC to find the needed VCCO_14, sets VCCO_14 to the needed value and powers-up the FPGA, grabs the appropriate bitstream, and uses this bitstream to configure the FPGA (see Fig 2-2 Slave Serial in UG470).

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Registered: ‎09-17-2018

Re: Bank 14 reconfiguration of VCCO, Artix 7

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My words come back to haunt me,

As long as you use an IO standard like LVCMOS, with a strength somewhere in the middle (like 8 ma), you could reconfigure from 3.3v to 2.5v or 2.5v to 3.3v without having any difficult signal integrity issues.  That said, I would be sure you can change the voltage without dropping it altogether.

l.e.o.

(aka Austin)

308 Views
Registered: ‎01-22-2015

Re: Bank 14 reconfiguration of VCCO, Artix 7

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@lowearthorbit  Austin! -great to have you back with us.

 

@gilessj 

Your job becomes much easier if you use a larger FPGA (ie. one where you can move all FMC connections out of the banks needed for FPGA configuration).  You’re maxed out on IO for the Artix-7 with the 1156 package.  However, you can get more IO by moving to the Virtex-7 which has 1761 and 1930 packages.

You’ll find that the Xilinx AC701 board has an Artix-7 and FMC connectors - but bank-14 pins are not used for FMC.  Initially on the AC701, most of the FPGA is powered-up (including bank-14) with fixed values of VCCO.  Then, the FPGA is configured.  Then, IO from bank-14 interrogates the FMC bus to find the needed value for VADJ.  Then, an adjustable power supply on the AC701 is set to produce the needed VADJ and (rather amazingly in my mind) the rest of the FPGA is power-up using VCCO=VADJ for banks connected to FMC (see page 66 of UG952(v1.4) for more details).

All this to tell you that I am not so sure about the need for separate bitstreams that I mentioned earlier.  UG471 clearly states, “The VCCO voltage must match the requirements for the I/O standards that have been assigned to the I/O bank. An incorrect VCCO voltage can result in loss of functionality or damage to the device.”  However, I kinda think there are exceptions to this since I doubt that users of the AC701 board are changing bitstreams in response to a change in VADJ.

Unless Austin has some guidance on this, I suggest that you open another post that specifically asks about use of VADJ on the AC701 board and whether the bitstream must be changed when VADJ changes.

Mark

Visitor gilessj
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Registered: ‎10-15-2019

Re: Bank 14 reconfiguration of VCCO, Artix 7

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Mark,

Now I don't know what I was thinking... Of course the bitstream has to match the signal standard!

For my specific design, this poses some interesting consequences (and possibly a workaround)... Since there needs to be manual intervention in setting up the correct bitstream for specific cards, one could pre-configure this bank voltage via DIP switches. This would violate Vita57, but in order to meet a fully automated process for bank voltage configuration, we would indeed need to have a separate processor for IPMI.

I did consider a separate MCU, but we decided to keep things as tight as possible (significant mechanical constraints). Even an ATTINY would be enough to handle this interface most likely, so I really should revisit that.

Austin, thank you for chiming in! In this case, we would need a configuration that would allow us to switch between single and differential signaling standards, so no dice on this concept.

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Visitor gilessj
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Registered: ‎10-15-2019

Re: Bank 14 reconfiguration of VCCO, Artix 7

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I really do believe they have to change the bitstream in order to accommodate various FMCs, even if the signaling standard is identical. IIRC, VITA57 dictates that VCCO and VADJ are identical (on the carrier card, VADJ is routed to VCCO as well as to the VADJ pins on the FMC). One thing to keep in mind is that FMCs are DEFINITELY not hot-swapped, so configuration will only happen at power-up. With the garden variety of FMCs in my office right now, I very much doubt that any one of them could use an identical bitstream.
As for moving up to the Virtex, that would be ideal; however, it is very likely that 100+ of these will get made, which will represent a significant cost increase for the facility.
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Registered: ‎01-22-2015

Re: Bank 14 reconfiguration of VCCO, Artix 7

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I really do believe they have to change the bitstream in order to accommodate various FMCs....
Keep believing this!   My trusted advisors say it is true - and that not changing the bitstream risks damage or reduced life of the FPGA.

  

187 Views
Registered: ‎09-17-2018

Re: Bank 14 reconfiguration of VCCO, Artix 7

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Damage is covered in Table 1.

It is really difficult to damage a device.  They are designed to be tough (unlike an ASIC with the minimum required).  So, let us not scare folks, OK?  We are engineers.  We read data sheets.  We design to requirements.  We stay out of the areas where damage will occur.  Literally, changing bits can hardly ever blow something up.  There are design rule checks in the bitgen to prevent this.  I tell my students to observe the ESD handling rules religiously, but be otherwise fearless with the tools and their design. I have seen clever designs do great things.  Be creative, follow the recommended values in Table 2, and avoid the abs max in Table 1.

l.e.o.

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