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Visitor
Visitor
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Registered: ‎12-27-2019

Behaviour of FlipFlops if fed by BUFGCE clock

 

Hello. I try to create a circuit that toggles between one and zero every time a press a push button. I synchronize the input with a slow running clock (slow_clk in the schematic) which runs at 1 Hz. On the left side you see the output of a clock divider (uses a counter and a BUFGCE). I used it because another post recommended to use BUFGCE buffers for clock division. It divides a 5 Mhz clock by 5 Million produce a one Hz output. It works: I output the clock on a led pin on my evaluation board (basys 3) and see the led blinking at a rate of one Hertz.

But I'm able to toggle between 1 and 0 on the complete high phase of slow_clk. I expected the circuit to only toggle the value of the tmp_reg (dout) on the rising edge of slow_clk. Because these flip-flops should be edge triggered. This behaviour only occurs if I use a BUFGCE. If I just use toggle register instead of a BUFGCE the circuit behaves like expected. (Toggles only on rising edge and have a delay of 2 clocks). This circuit toggles everytime the clock is high (without any delay) Do you have any idea why this happens?

design.png

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Moderator
Moderator
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Registered: ‎04-18-2011

Re: Behaviour of FlipFlops if fed by BUFGCE clock

Does it work in simulation?

Can you share the rtl code you use to do this? 

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Behaviour of FlipFlops if fed by BUFGCE clock

What chip does your board have on it ?
does that chip support the BUFGCE_DIV ?
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