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Visitor
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Registered: ‎04-07-2020

Can I leave al DDR (including all VCCO_DDR) pins unconnected?

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Hi,

I would like to confirm this detail:  If I don't use external DDR memory chips in my design, can I leave all VCCO_DDR pins unconnected? 

What about all other pins related to DDR (including VREFs, CLKs, etc.)?  can those also be unconnected?

From what I understand in the datasheet and TRM, it sounds like I can;  but the documents don't state it explicitly.

In case it makes any difference, I'm using the XC7Z014S-CLG400.

Thanks,
Carlos
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Explorer
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Registered: ‎03-31-2016

Have a look at the PCB Design guide again:

Unused DDR Memory
When no PS DDR memory is used, VCCO_DDR should be tied to VCCPAUX. PS_DDR_VREF0/1
and PS_DDR_VRN/P should be left floating.

No you can't leave everything completely floating.  You should do a careful reading of all the documentation to ensure that nothing else needs to be tied any special way.

That said are you sure your application only needs the OCM?  If it is really that small a larger Artix, so you can use the BRAM as internal memory, with a soft-core Cortex M or Microblaze is something you should consider. 

Pretty much any use case that needs an Cortex A9 is going to need external memory.

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Registered: ‎07-23-2019

 

First, it makes little sense. If you have a SoC, it's to use the PS, otherwise you can just use an Artix-7.

In theory, yes, the PS-DDR is only used by the PS, so without DDR, no PS

But...

I think (I mean, you should check) that with the Zynq, you always load the PL with the bootloader that runs on the PS and I assume it uses the DDR (it might just run on the OCM, not sure). So you might not be able to load anything without the PS and its DDR. Again, not sure about that. With Ultrascale+, definitely, you need the bootloader and the PS to load the PL.

 

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Registered: ‎04-07-2020

@archangel-lightworks wrote:

 

If you have a SoC, it's to use the PS [ ··· ]


Well yes, of course I will use the PS.  My thought process is that using the PS and using additional memory (in the form of external DDR) are two separate things  (as in, the PS does have OCM and it all can work with that, with the DDR being optional?  Maybe I am missing something?)

Carlos
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Explorer
Explorer
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Registered: ‎03-31-2016

Have a look at the PCB Design guide again:

Unused DDR Memory
When no PS DDR memory is used, VCCO_DDR should be tied to VCCPAUX. PS_DDR_VREF0/1
and PS_DDR_VRN/P should be left floating.

No you can't leave everything completely floating.  You should do a careful reading of all the documentation to ensure that nothing else needs to be tied any special way.

That said are you sure your application only needs the OCM?  If it is really that small a larger Artix, so you can use the BRAM as internal memory, with a soft-core Cortex M or Microblaze is something you should consider. 

Pretty much any use case that needs an Cortex A9 is going to need external memory.

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Registered: ‎04-07-2020

@necare81 wrote:

Have a look at the PCB Design guide again:

[ ··· ]

D'oh!!   I had downloaded and partially read the PCB Design Guide...  But it didn't occur to me that the answer to this detail would be there!  Thanks for pointing this out!

Then again, maybe I should consider adding some DDR memory!

Thanks,
Carlos
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