03-25-2020 10:56 AM
The existing PCB was designed based on the decoupling requirements for an XC7A35T. Desire is to migrate to an XC7A100T without PCB changes. Per the UG this means they need to add the following:
1 @ 100uF on Vccint
4 @ 4.7uF on Vccint
5 @ 0.47uF on Vccint
1 @ 0.47uF on Vccbram
In some cases BOM changes can be made for example using a 10uF where a 4.7uF was installed, but a 220uF cap will not fit on the footprint for the existing 100uF cap.
The design is not full and is being migrated because more BRAM is needed.
Should we increase the capacitance values where possible to allow for the increase in static and BRAM power consumption, or will that violate the desired frequency response of the bypass caps?
Any guidance that can be provided would be greatly appreciated.
03-25-2020 01:07 PM
03-25-2020 11:02 AM
03-25-2020 11:21 AM
Thanks for the feedback. All caps are ceramic. No simulation options here for the power distrobution. I would think that would be a mess to model based on having to model a complex FPGA design and the demands it creates on all of the rails.
So your recommendation would be to change the 4.7uF caps to 10uF and the 0.47uF to 1uF to more closely match the UG table for the XC7A100T and see how the system performs? We can measure noise, look at rails during power up and during design operation and the like...
03-25-2020 01:07 PM
03-25-2020 02:41 PM
Thanks. To close the loop here I received some additional guidance through other channels that I thought might be good to add to this posting.
- the amount of decoupling is a direct function of the magnitude of step load seen in their design
- the values recommended in the PCB guide are worst case
- use XPE to calculate the current loading in a 7A35T and compare that to the 7A100T with added feature requirements. The magnitude of this difference can be used to make a reasonable guess regarding additional bypass capacitance
- run a clock out to a pin so you can look at the system “system jitter” on the design
I appreciate your help.