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Visitor whyphy
Visitor
369 Views
Registered: ‎06-21-2019

Consequences of using fabric for clock mux?

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Working on a design in Series 7 (Kintex) where a high-number of clocks (> 10) need to be muxed onto a single BUFG.  The BUFG will be used to drive limited logic inernally, and an ODDR to output the selected clock.

Using clocking resources (BUFGCTRL) is not an acceptable solution given the high number required.  

In this design, switching between clocks is not expected to be hitless, or glitch-free.

So what is the downside of using fabric logic to implement the MUX in this scenario? 

 

 

 

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Historian
Historian
350 Views
Registered: ‎01-23-2009

Re: Consequences of using fabric for clock mux?

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The two main disadvantages are:

  • The phase of the MUXed clock is almost completely unknown with respect to each input clock
    • The fabric routing of the clock will vary from implementation to implementation, and will be highly process, voltage and temperature (PVT) dependent
    • This may not matter if you are not using this to clock any input interface, or for any system synchronous output interface
  • The MUXed clock will have more jitter due to the fact that it goes through the general fabric routing area
    • This jitter is not quantified, but may be significant...

Avrum

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5 Replies
Historian
Historian
351 Views
Registered: ‎01-23-2009

Re: Consequences of using fabric for clock mux?

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The two main disadvantages are:

  • The phase of the MUXed clock is almost completely unknown with respect to each input clock
    • The fabric routing of the clock will vary from implementation to implementation, and will be highly process, voltage and temperature (PVT) dependent
    • This may not matter if you are not using this to clock any input interface, or for any system synchronous output interface
  • The MUXed clock will have more jitter due to the fact that it goes through the general fabric routing area
    • This jitter is not quantified, but may be significant...

Avrum

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Visitor whyphy
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336 Views
Registered: ‎06-21-2019

Re: Consequences of using fabric for clock mux?

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In this case, the phase relationship between the input clock and the BUFG doesn't matter.  Ultimately, this is just a really big clock mux.  Multiple inputs to the FPGA, one output. 

The only disadvantage would then be the higher jitter.  The output is expected to be a slow clock (most likely 8KHz), and extra jitter is probably not an issue.  

Would the input clocks need to be on CC (clock capable) pins in this scenario?   The inputs will be driving a LUT, which will then be driving the BUFG.  

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Scholar dgisselq
Scholar
318 Views
Registered: ‎05-21-2015

Re: Consequences of using fabric for clock mux?

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@whyphy,

Wait, you're only trying to create an 8kHz clock?  Why not just use a 100MHz clock (or whatever high speed system clock is appropriate) and clock enables?  You'd then get 1) lower jitter, 2) better I/O performance, 3) simplified clock domain crossings, and 4) known phase relationships throughout the entire FPGA, and more.

So, instead of ...

always @(posedge clk_8kHz)
    some_logic;

you'd instead write,

always @(posedge system_clock)
if (clock_enable_8kHz)
    some_logic;

It's so much simpler to do, I can't imagine a reason why you wouldn't want to,

Dan

Visitor whyphy
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Registered: ‎06-21-2019

Re: Consequences of using fabric for clock mux?

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8kHz is the approximate frequency of the output. It is actually a divided down version of the selected clock.  

 

 

 

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Scholar dgisselq
Scholar
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Registered: ‎05-21-2015

Re: Consequences of using fabric for clock mux?

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It'd be a whole lot easier to just generate that clock from logic by dividing down a system clock, than it would be to attempt to make transitions on and use that wire as a "clock" within your FPGA.

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