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Observer
Observer
4,727 Views
Registered: ‎11-26-2014

DSP/LUT area ratio on 7 series

Hello,

 

 

DSP slices in FPGAs (series 7) can be used to substitute LUTs to reduce area an increase the performance of the design, but what is the DSP/LUT area ratio between there two blocks?

 

 

 

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Guide
Guide
4,711 Views
Registered: ‎01-23-2009

I kind of have to ask the question "why do you care?"

 

The concept of area is one that affects chip construction, not FPGA utilization. Each member of the 7 series family is already constructed, and hence has a fixed number of LUTs and a fixed number of DSP48 cells. The area of these (and other things) determines the cost of the FPGA. While you can target some logic to either DSP48 or LUTs, the resources themselves are fixed - the FPGA contains a certain number of LUTs and a certain number of DSP48. You cannot (for example) get more LUTs available from the FPGA by leaving DSP48 cells unused (or vice versa). This is as opposed to (for example) LUTs vs. distributed RAM (SelectRAM) cells, which are the same resource on the die - using more distributed RAMs leaves less LUTs available for logic.

 

Given that this is the case, the area ratio between these resources is somewhat irrelevant. What you need to do now is find a way of implementing your design in the cheapest FPGA possible - ideally this means leaving as little unused resources available. If, for example, in a particular FPGA you are using 90% of the LUTs and 40% of the DSP48 cells, you could ask yourself "If I move more logic from LUTs to DSP48 cells, could I fit in a smaller (i.e. cheaper)  FPGA?". If the answer to this is "yes", then go for it. If the answer is "no", then any further optimizations you do would simply be moving logic from one unused resource to the other. Unless this has a secondary effect (like helping timing closure or reducing power - either of which could be true), then you are done. At no point does the area ratio of the DSP48 to LUTs play into this decision process...

 

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