For page 5 and 17 of https://www.xilinx.com/support/documentation/application_notes/xapp1064.pdf , I have few questions.1) In https://github.com/mithro/soft-utmi/blob/master/hdl/third_party/XAPP1064-serdes-macros/Verilog_Source/Macros/serdes_1_to_n_data_ddr_s8_diff.v#L216-L256 and Figure 6, may I know how does this phase detection state machine works ? and which portion of the rest of the code belongs to calibration state machine ?2) For figure 18, what do "USE_DOUBLER=TRUE" and "I_INVERT=TRUE" mean ? What is the purpose of the dotted line labelled as "Serdes Strobe" ? 3) For Figure 6, how does the signal "User BITSLIP" work for data reception ? In the upper block, why is "Master IDELAY" connected to two-inputs "BUFIO2_2CLK" ?
4) How do I turn on DDR mode for ISERDES primitive ? and how is this different from IDDR primitive ?