07-02-2018 10:11 AM
Hi - I've been trying to implement a design based on the XADC demo for the Arty z7-10, but I've been having difficulty figuring out exactly how to properly switch between 3 channels (VP/VN, A0 and A1) when in DRP mode with the channel sequencer. I've attempted to use the switches to alternate channels as in the example design, though what I would ultimately like to do is poll each channel at a regular timed interval. Attached are my modifications to the example verilog source, any help would be greatly appreciated.
07-03-2018 12:45 AM
The Automatic channel sequencer will sequence through the selected channels one after the next and issue an end of conversion pulse, EOC, when it has converted it.
You should take some time to read UG480 to understand the XADC timing.
07-03-2018 07:21 AM
Thank you for your reply klumsde. I have been reading through the manual - though I guess what I am a bit confused about is how to acquire data from only one channel at a time. It seems that anything I have implemented has either no channels active or several active all at once.
07-03-2018 01:04 PM