03-08-2020 10:34 AM
I am using one of the virtex ultrascale+ FPGA in our product. Our expected FPGA utilization is around 50%. The system clock is 500MHz.
Is it possible to get timing clean design having multiple paths of upto 7 logic levels in between 2 flip-flops ?
03-08-2020 07:33 PM
Our FPGA is receiving data at very high throughput of 32Gbps over 6 lanes..
So, we are running our internal FPGA logic at 500MHz.
I saw that tool is able to meet timing if logic levels are 4-5. But difficult to meet the timing with 7 logic levels.
03-09-2020 04:04 AM - edited 03-09-2020 04:05 AM
Can you not just de-mux the incoming data and process the data at a lower speed with a wider bus?
For example, 25Gb Mac outputs data on 64 bit AXI bus @390Mhz. To make life easier you can switch down to a ~195Mhz with 128bit bus. Data rate is the same