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Newbie
Newbie
233 Views
Registered: ‎07-05-2018

Does 7 Logic Levels synthesizable in virtex ultrascale+ FPGA at 500MHz with 50% logic utilization

Hi,

 

I am using one of the virtex ultrascale+ FPGA in our product. Our expected FPGA utilization is around 50%. The system clock is 500MHz.

 

Is it possible to get timing clean design having multiple paths of upto 7 logic levels in between 2 flip-flops ?

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Scholar
Scholar
207 Views
Registered: ‎08-01-2012

Re: Does 7 Logic Levels synthesizable in virtex ultrascale+ FPGA at 500MHz with 50% logic utilization

Id say 500 Mhz with a single logic level would be ambitious. Let alone 7.

Why do you need such a high system clock?

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Newbie
Newbie
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Registered: ‎07-05-2018

Re: Does 7 Logic Levels synthesizable in virtex ultrascale+ FPGA at 500MHz with 50% logic utilization

Hi Richard,

 

Our FPGA is receiving data at very high throughput of 32Gbps over 6 lanes..

So, we are running our internal FPGA logic at 500MHz.

 

I saw that tool is able to meet timing if logic levels are 4-5. But difficult to meet the timing with 7 logic levels.

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Scholar
Scholar
136 Views
Registered: ‎08-01-2012

Re: Does 7 Logic Levels synthesizable in virtex ultrascale+ FPGA at 500MHz with 50% logic utilization

Can you not just de-mux the incoming data and process the data at a lower speed with a wider bus?

For example, 25Gb Mac outputs data on 64 bit AXI bus @390Mhz. To make life easier you can switch down to a ~195Mhz with 128bit bus. Data rate is the same

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