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Visitor jimian_tw
Visitor
7,221 Views
Registered: ‎08-22-2016

Does Virtex-7 GTH supports USB3 LFPS and receiver detect?

I'm using the Virtex-7 GTH IP to implement a USB3.1 PHY that supports both 5G and 10G data rate.

Now I'm able to transmit and receive USB3.1 data packets using this PHY in my simulation, but I also want to add support to the following functions as well:

  • Transmit and receive LFPS
  • Perform Rx termination detect

From the Virtex-7 transceivers manual, I found GTH supports OOB signaling such as PCIe beacon, which is similar to USB3.1 LFPS.

However, I found it has a limitation- GTH transmits OOB beacon only if TXPD=P2. 

According to the PIPE spec, USB LPFS can be transmitted during all power down states.

I also found GTH supports PCIe Rx termination detection mechanism, but I'm not sure if it is compatible with USB3/3.1.

 

I'd like to know if Virtex-7 GT transceivers can support USB3 LFPS and receiver detect, or should I need to implement them using other IPs or our own design?

Thank you!

 

 

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10 Replies
Xilinx Employee
Xilinx Employee
7,218 Views
Registered: ‎08-01-2008

Re: Does Virtex-7 GTH supports USB3 LFPS and receiver detect?

USB is not on the plan for support in any transceiver family. You could use the CDR settings from AR#53364 since SATA also has similar SSC specification but we do not really know the protocol compliance can be achieved since the transceivers are not characterized for this protocol.

check this alliance partner core

http://www.xilinx.com/products/intellectual-property/1-8dyf-1597.html
Thanks and Regards
Balkrishan
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Visitor jimian_tw
Visitor
7,209 Views
Registered: ‎08-22-2016

Re: Does Virtex-7 GTH supports USB3 LFPS and receiver detect?


@balkris wrote:
USB is not on the plan for support in any transceiver family. You could use the CDR settings from AR#53364 since SATA also has similar SSC specification but we do not really know the protocol compliance can be achieved since the transceivers are not characterized for this protocol.

check this alliance partner core

http://www.xilinx.com/products/intellectual-property/1-8dyf-1597.html

Do you have any recommendation for CDR setting at 5/10G bit rate with SSC, as required by USB3.1 spec?

From the AR#53364 I can only find settings for SATA 6G at most, but my PHY has to support USB 5G/10G data rate.

 

Also, I'd like to know if I design a USB3 LFPS generator by myself, how can I integrate it into my GTH instance so that I can use the TXP/N output ports from GTH to output LFPS signal as well?

(That is, I'd like to bypass the Tx OOB sub-module in GTH and use my own instead.)

 

Thank you! 

 

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Xilinx Employee
Xilinx Employee
7,187 Views
Registered: ‎08-01-2008

Re: Does Virtex-7 GTH supports USB3 LFPS and receiver detect?

check this ARs
http://www.xilinx.com/support/answers/63869.html
Thanks and Regards
Balkrishan
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Visitor jimian_tw
Visitor
7,162 Views
Registered: ‎08-22-2016

Re: Does Virtex-7 GTH supports USB3 LFPS and receiver detect?

I later re-configured my RocketIO GTH-based USB3 PHY so that it operates in PCIe mode, in order to utilize its Tx OOB beacon function to send LFPS.

However, I found the pulse width of the OOB beacon generated by GTH is 2ns, as shown in the following simulation waveform:

(PS: TDLFPSEN is from my other logic that indicates LFPS output enable.)

Tx Beacon from GTH

Although this fits the PCIe spec, that states the pulse width of the beacon can be from 2ns to 16us, a 2ns width is too short for USB3 LFPS, whose minimum pulse width is 20 ns.

I'd like to know if it is possible to tweak the pulse width of the PCIe beacon from GTH Tx.

Thank you!

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Moderator
Moderator
7,109 Views
Registered: ‎02-16-2010

Re: Does Virtex-7 GTH supports USB3 LFPS and receiver detect?

Can you use the fabric logic to generate the beacon for required width?
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Visitor jimian_tw
Visitor
7,047 Views
Registered: ‎08-22-2016

Re: Does Virtex-7 GTH supports USB3 LFPS and receiver detect?


@venkata wrote:
Can you use the fabric logic to generate the beacon for required width?

I'd like to know if I decide to generate the beacon/LFPS myself, how should I incorporate my custom logic into GTH design?

For example:

rocketio custom beacon

In the above example, I use my custom logic to generate my beacon to fit the USB3 LFPS spec, and then send its output to a MUX's 1 input port.

The MUX's 0 input will be from the original TXP/N from GTH.

If LFPS output is enabled, then the MUX will select the output from my beacon logic to output, otherwise it still selects the original TXP/N from GTH.

However, I remember RocketIO TXP/N output ports are dedicated analog IO ports in FPGA, and they have dedicated routes.

But my custom logic will produce digital output signals.

So I'm not sure if I can directly mux my digital output with the analog TXP/N from GTH...

 

 

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Moderator
Moderator
7,011 Views
Registered: ‎02-16-2010

Re: Does Virtex-7 GTH supports USB3 LFPS and receiver detect?

You need to put the mux at the parallel data interface side.
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Visitor jimian_tw
Visitor
6,995 Views
Registered: ‎08-22-2016

Re: Does Virtex-7 GTH supports USB3 LFPS and receiver detect?


@venkata wrote:
You need to put the mux at the parallel data interface side.

Here is the basic wave form of USB3 LFPS, from the USB3 spec:

LFPS_fig.png

LFPS is composed of a tBurst (periodic 0/1) and an electrical idle phase. The period of the burst phase (tPeriod) ranges from 20 ns to 100(Gen1)/80(Gen2) ns.

I think I'm able to construct a special parallel TXDATA input that will result in the required LFPS pulse width on TXP/N, although whether it conforms with the electrical spec of LFPS needs to be further checked.

However, I don't know how to force an electrical idle (i.e. both TXP and TXN are 0) on the TXP/N of GTH...

(Usually TXP=0 but TXN=1 if TXDATA=0)

 

PS: Here is the electrical requirements for LFPS-

LFPS electrical requirement

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Visitor jimian_tw
Visitor
6,984 Views
Registered: ‎08-22-2016

Re: Does Virtex-7 GTH supports USB3 LFPS and receiver detect?

By the way, I found the GTH supports two Tx EQ configuration- TXPOSTCURSOR and TXPRECURSOR.

They are both "pre-emphasis control" according to the Xilinx GTH documentation.

In the USB3 spec, it describes that the transmitter should support pre-cursor pre-shoot and post-cursor de-emphasis.

The definition of pre-shoot and de-emphasis is as shown in the followng figure:

(Note: pre-cursor is Vc and post-cursor is Vb)

USB3 Tx Eq example

 

I'd like to know how to correspond the Preshoot and De-emphasis value defined in the USB3 spec with the emphasis value chosen from TXPRECURSOR/TXPOSTCURSOR.

Thanks!

 

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Explorer
Explorer
2,185 Views
Registered: ‎07-10-2013

Re: Does Virtex-7 GTH supports USB3 LFPS and receiver detect?

jimian_tw,

 

Out of curiosity, what xcvr settings did you use for 10Gbps RX?  How did you determine what settings were proper and optimal for handling the SSC-modulated incoming serial data?  How did you verify that your design did in fact handle SSC-modulated incoming serial data properly?

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