Driving the HP Bank GPIO with 1.8V signal before the VCCO is powered upto 1.8V: Kintex7 160T FPGA

[deepaknielit]

Hi,

The answer recorded 'AR# 45985' is all about driving FPGA with the 3.3V logic signal before VCCO is powered.
I have gone through it and understood the same.

But I am still confused about what happens when 1.8V logic signal drives FPGA HP I/O before any of the FPGA Power rails(VCCINT, VCCAUX/AUXIO, VCCO_HP, VCCO_HR) are powered.

Since here there is no 2.625V violation of TVCCO2VCCAUX, my conclusions are as follows.

1. FPGA HP I/Os will not get damaged if clamping diode current is maintained less than 10mA
2. There is no need to use any resistor at VCCO_HP pins to limit the voltage less than 2.625V

Kindly verify the correctness of above-listed conclusion. So I can proceed without incorporating any additional protection circuits when one or two HP GPIO are driven before the FPGA is powered ON.

Regards
DEEPAK V 

[drjohnsmith · Accepted solution]

Its all about time.

Are the fpga inputs driven for years before the fpga power is applied , or is it milli seconds as power comes up ?

In the former, Id be looking at some sort of protection, probably sacrificial fet array, 

   in the latter, I'd not worry powering 1v8 into a 1v8 input,

[deepaknielit]

Hi @drjohnsmith

Here in my case, it happens only for few seconds during system Power ON. And as you suggested I will proceed without any additional protection.

Thank you for your valuable time.

Regards
DEEPAK V