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Registered: ‎06-06-2017

Driving unpowered Artix-7 FPGA pin

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There are many posts talking about driving unpowered 7-series FPGA, but none of them resolved my case. I would like to know if an Artix-7 FPGA will be damaged if one of its IO pin is driving with 3.3V while the FPGA is unpowered. The 3.3V supply is connected to the FPGA with 1100 ohm series resistor. Schematic shown below.

xilinxForumPost_unpoweredFPGA.PNG

 

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Registered: ‎01-22-2015

@eramos01 

Is this circuit is not violating TVCCO2VCCAUX specification described on page 8 of DS181?

Kudos to you for seeing this!  You are correct that your circuit(s) might cause the TVCCO2VCCAUX specification to be violated.   

However, the quiescent current for the Artix-7 VCCO rail is typically 1mA (see Table 5 of DS181(v1.25)) - and startup current of VCCO (see Table 6) for a bank is 40mA.  So, at powerup, the VCCO rail in the FPGA will try to draw this 41mA through the 1100 ohms of your circuit, which will drop the voltage to near zero.  Even 1mA draw from the VCCO rail through 1100 ohms will drop 3.3V to 2.2V.  You can do more of this kind of analysis if you have multiple versions of your circuit on a bank.

Ideally, the VCC=3.3V for your circuit is also the VCCO for the FPGA bank that connects to your circuit.  Then, if your supplies are ramping up per Table 7 of DS181(v1.25), the TVCCO2VCCAUX specification should not be violated.

 

There will be more than one circuit similar to this connected to the FPGA. To not exceed the 200mA limit per bank, I plan to spread them to different banks. What are your thoughts on this?

Yes, that should satisfy the Table 2 footnote-8 requirement from DS181.

 

A good way to avoid all these worries is to design your board so that the VCC=3.3V for your circuit powers-up after the FPGA powers-up, and powers-down before the FPGA powers-down.  The power-up/down of circuits connected to an FPGA is often a concern and falls under the topic of hot-swapping the FPGA.  See XAPP251 , XAP1311 and AR#44225 for more information.

Cheers,
Mark

 

 

 

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Registered: ‎01-22-2015

@eramos01 

The Artix-7 IO have clamping diodes to VCCO and GND with a threshold voltage of between 0.43 and 0.64V

So, when the Artix-7 is unpowered (ie. VCCO=0V) then a current of (3.3-0.43)/(1000 + 100) = 2.6mA could flow through your circuit and through the Arix-7 clamping diode to the unpowered VCCO rail.  See <this> post for more discussion.

Table 2 of the Artix-7 datasheet, DS181(v1.25), says that "Maximum current, Iin, through any pin in a powered or unpowered bank when forward biasing the clamp diode." must be less than 10mA.  So, the 2.6mA from your circuit should not damage the Artix-7 IO.  However, if you have placed your circuit on more than one IO pin then be sure to read footnote (8) to Table 2 in DS181.

Cheers,
Mark

 

Visitor
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Registered: ‎06-06-2017

markg@prosensing.com 

Hi Mark, thanks for clearing this for me.

Is this circuit is not violating TVCCO2VCCAUX specification described on page 8 of DS181? I ask because if the diode is forward biased VCCO rail will be powered.

There will be more than one circuit similar to this connected to the FPGA. To not exceed the 200mA limit per bank, I plan to spread them to different banks. What are your thoughts on this?

Thanks
Erickson

439 Views
Registered: ‎01-22-2015

@eramos01 

Is this circuit is not violating TVCCO2VCCAUX specification described on page 8 of DS181?

Kudos to you for seeing this!  You are correct that your circuit(s) might cause the TVCCO2VCCAUX specification to be violated.   

However, the quiescent current for the Artix-7 VCCO rail is typically 1mA (see Table 5 of DS181(v1.25)) - and startup current of VCCO (see Table 6) for a bank is 40mA.  So, at powerup, the VCCO rail in the FPGA will try to draw this 41mA through the 1100 ohms of your circuit, which will drop the voltage to near zero.  Even 1mA draw from the VCCO rail through 1100 ohms will drop 3.3V to 2.2V.  You can do more of this kind of analysis if you have multiple versions of your circuit on a bank.

Ideally, the VCC=3.3V for your circuit is also the VCCO for the FPGA bank that connects to your circuit.  Then, if your supplies are ramping up per Table 7 of DS181(v1.25), the TVCCO2VCCAUX specification should not be violated.

 

There will be more than one circuit similar to this connected to the FPGA. To not exceed the 200mA limit per bank, I plan to spread them to different banks. What are your thoughts on this?

Yes, that should satisfy the Table 2 footnote-8 requirement from DS181.

 

A good way to avoid all these worries is to design your board so that the VCC=3.3V for your circuit powers-up after the FPGA powers-up, and powers-down before the FPGA powers-down.  The power-up/down of circuits connected to an FPGA is often a concern and falls under the topic of hot-swapping the FPGA.  See XAPP251 , XAP1311 and AR#44225 for more information.

Cheers,
Mark

 

 

 

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Visitor
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Registered: ‎06-06-2017

markg@prosensing.com 

All kudos to you for helping out. I appreciate it.


We are designing a custom board that will interface with external boards that will have access to the FPGA pins. The time external board is powered is out of our control, this is the reason why we are having this issue.

We will use the information you provided to us to make a decision on how to move forward.


Thanks

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