06-11-2021 01:26 AM - edited 06-11-2021 01:27 AM
i looked datasheet, Bram can work at 200 mghz but there is some requirements,
for example :
Fmax_Bram_RF - Block RAM (read first,
performance mode) when
in SDP RF mode but no
address overlap between
port A and port B
but i am using vivado ip itegrator to generate Bram and there i cant change Write first to Read first Mode for B port, this field is blocked.
for A port where i read from Bram, there is available this field to change
06-11-2021 05:01 AM
From the datasheet, if you are using a 1.0V 7-series part, all modes look like they will work at or above 300MHz. Performance may be limited by the design at 200MHz, but probably not by the BRAM. The only way to know is to build the design, but the BRAMs should work. Caveats:
1. Sometimes to make timing, you need to use the additional output registers.
2.Large arrays of BRAMs can have routing delays. .