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Observer echristian
Observer
7,773 Views
Registered: ‎02-10-2015

FPGA master xdc question with vhdl

if you have the following pseudo code :

 

Can you have sub componenst ports map to fpga pins? If so,what would i do in master xdc file?

 

entity ScrollingSevenSegmentDisplay

port(

         msgIn : std_logic_vector(width -1 downto 0)

         refreshSeconds : integer;

 )

arch of ScrollingSevenSegmentDisplay

is

component SevenSegmentDisplay

(

   an     : out           std_logic_vector(7 downto 0);

   seg   : out           std_logic_vector(6 downto 0);

   dp     : out           std_logic

);

 

begin

 

comp_seven : SevenSegmentDisplay

Thanks

Eddie

 

......

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6 Replies
Observer echristian
Observer
7,762 Views
Registered: ‎02-10-2015

Re: FPGA master xdc question with vhdl

can i use "all_outputs" ?

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Scholar pratham
Scholar
7,754 Views
Registered: ‎06-05-2013

Re: FPGA master xdc question with vhdl

Hi @echristian 

 

Yes, You can do.

Please see the help from vivado tcl console. all_outputs -help

all_outputs -help
all_outputs

Description:
Get a list of all output ports in the current design

Syntax:
all_outputs [-quiet] [-verbose]

Returns:
list of port objects

Usage:
Name Description
-------------------------------------------------------------
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution

Categories:
SDC, XDC

Description:

Returns a list of all output port objects that have been declared in the
current design.

To get a list of specific outputs in the design, use the get_ports command,
or use the filter command to filter the results returned by all_outputs.

The all_outputs command is scoped to return the objects hierarchically,
from the top-level of the design or from the level of the current instance.
By default the current instance is defined as the top level of the design,
but can be changed by using the current_instance command.


Arguments:

-quiet - (Optional) Execute the command quietly, returning no messages from
the command. The command also returns TCL_OK regardless of any errors
encountered during execution.

Note: Any errors encountered on the command-line, while launching the
command, will be returned. Only errors occurring inside the command will be
trapped.

-verbose - (Optional) Temporarily override any message limits and return
all messages from this command.

Note: Message limits can be defined with the set_msg_config command.


Examples:

The following example returns all the output ports in the current design:

all_outputs

The following example sets the output delay for all outputs in the design:

set_output_delay 5 -clock REFCLK [all_outputs]


See Also:

* all_inputs
* current_instance
* filter
* get_ports
* set_output_delay

-Pratham

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Observer echristian
Observer
7,728 Views
Registered: ‎02-10-2015

Re: FPGA master xdc question with vhdl

I have looked at those tcl commands , but still dont quite understand how to map child component ports in xdc file:

 

here is at small piece of code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity switches is
Port (
sw : in std_logic_vector(7 downto 0)
);
end switches;

architecture Behavioral of switches is

component sevenSeg is
Port (
xx : in STD_LOGIC_VECTOR(7 downto 0);
an : out STD_LOGIC_VECTOR(7 downto 0);
seg : out STD_LOGIC_VECTOR(6 downto 0);
dp : out STD_LOGIC
);
end component;

signal seg :STD_LOGIC_VECTOR(6 downto 0);
signal dp : std_logic;
signal an : STD_LOGIC_VECTOR(7 downto 0);
begin

seven_ins : sevenSeg
port map(
xx =>sw,
an => an,
seg => seg,
dp => dp
);

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sevenSeg is
Port (
xx : in STD_LOGIC_VECTOR(7 downto 0);
an : out STD_LOGIC_VECTOR(7 downto 0);
seg : out STD_LOGIC_VECTOR(6 downto 0);
dp : out STD_LOGIC
);
end sevenSeg;

architecture Behavioral of sevenSeg is

begin
an <= xx;
seg <= "0011000";
dp <= '1';
end Behavioral;

 

 

 

 

and  here is the relevant xdc fpga ports(nexys4 ddr)

##7 segment display
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports {seg[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports {seg[1] }]; #IO_25_14 Sch=cb
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { seg[2] }]; #IO_25_15 Sch=cc
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { seg[3] }]; #IO_L17P_T2_A26_15 Sch=cd
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { seg[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { seg[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { seg[6] }]; #IO_L4P_T0_D04_14 Sch=cg

#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp

#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6]
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]

 

 

so what would be the syntax for lets say seg{0}?

 

 

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Observer echristian
Observer
7,722 Views
Registered: ‎02-10-2015

Re: FPGA master xdc question with vhdl

at the top of my xdc file the following commented lines exist:

 

## This file is a general .xdc for the Nexys4 DDR Rev. C
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

 

But it seems like from the docs you can map the ports to sub-modules?

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Explorer
Explorer
7,704 Views
Registered: ‎06-25-2014

Re: FPGA master xdc question with vhdl

So, what you are asking is can you create a FPGA pin mapped port from a buried instance port name without drilling that up through to the top of your HDL hierachcy?

 

If I understand you correctly, I did not think this was possible and would be interested to know if it can be done using Vivado!

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Observer echristian
Observer
7,692 Views
Registered: ‎02-10-2015

Re: FPGA master xdc question with vhdl

exactly. Can this be done?

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