09-01-2015 04:17 AM
i tried to implement TX direction on "v_smpte_uhdsdi_gtwiz" (from mange ip)
my ref clk gth_qpll0_ref_clk_p_in = 148.5Mhz
drpclk = 148.5Mhz
tx_mode = '01' - SD-SDI
tx_m_in = 1
gth_wiz_treset_all_in = asserted to '1' more then 1 cycle of drp clock
qpll0_lock = 1
but tx_userclk_out ouput is '0'!! - need to be 148.5Mhz
i dont why. if someone can help me with this. i will be more than happy [-:
09-01-2015 04:44 AM
I see that Qpll lock and gt reset done is not asserted in the simulations.
You need to simulate for longer time.
09-01-2015 05:12 AM
Is this with the core generated test bench or your own.
09-11-2015 11:56 AM