cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
8,571 Views
Registered: ‎11-02-2015

GTX's TX/RX I/O ports assignment

Hi,

 

I am using GT wizard example. Here I modified the exdes.v code, after modifing the code TX/RX are no longer remaining differential pair. And also I'm unable to assign to their I/0 ports. Where am I going wrong?

 

And also I couldn't able to assign TX_polarity port to push buttons.

 

Here I have attached my exdes.v file and snapshot.

 

Check lines 86-89 and 306-322.

 

Thank you 

vivado5.JPG
0 Kudos
4 Replies
Highlighted
Moderator
Moderator
8,569 Views
Registered: ‎02-16-2010

Re: GTX's TX/RX I/O ports assignment

txp/txn and rxp/rxn are the output/input of GT block. You cannot implement logical functions on this signals. You will need to implement any functionality at the parallel data side of the GT block.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Highlighted
Newbie
Newbie
8,133 Views
Registered: ‎01-25-2016

Re: GTX's TX/RX I/O ports assignment

Hi,

 

I understood that, we can not use the GTX/mgt pins of the Transceiver as GPIO.

 

Can I connect the txp/txn to rxp/rxn pins for loopback for production quality testing ? is there any design restriction?

 

please confirm.

 

Regards

Devraj

0 Kudos
Highlighted
Moderator
Moderator
8,116 Views
Registered: ‎02-16-2010

Re: GTX's TX/RX I/O ports assignment

There is Near end PMA loopback option to route the serial data going out from txp/txn to rxp/rxn. The loopback happens internal to the device.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
8,111 Views
Registered: ‎02-06-2013

Re: GTX's TX/RX I/O ports assignment

Hi

 

Yes it it possible to do external cable loopback to connect txp ->rxp and txn -> rxn

 

Refer Loopback section below doc for Transceiver internal loopback options

 

http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf

 

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos