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Explorer
Explorer
1,355 Views
Registered: ‎01-13-2018

How to disable FCLK_RESET0_N - ZYNQ

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I am wondering how to disable  FCLK_RESET0_N. I disable PL Fabric Clocks but still I see  FCLK_RESET0_N. Any idea how to disable this ? 

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Explorer
Explorer
1,499 Views
Registered: ‎01-13-2018

Re: How to disable FCLK_RESET0_N - ZYNQ

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: How to disable FCLK_RESET0_N - ZYNQ

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The solution is to just write the register directly.

/ assert FPGA Reset Signal
	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
    Xil_Out32(XSLCR_FPGA_RST_CTRL_ADDR, 0x0F);

    // ---

    // and release the FPGA Reset Signal
    Xil_Out32(XSLCR_FPGA_RST_CTRL_ADDR, 0x00);
    Xil_Out32(XSLCR_LOCK_ADDR, XSLCR_LOCK_CODE);

 

Thanks and Regards
Balkrishan
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Explorer
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Registered: ‎01-13-2018

Re: How to disable FCLK_RESET0_N - ZYNQ

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Untitled24.png
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