How to invert reset polarity ?

[bhawandeepsingh]

Hi.

I am working on a design on Zynq 7 series FPGA. We are using some divider and IFFT Logic-core blocks.

Earlier version of the IP used an Active high reset. Newer versions use Active low reset.

I am adding an inverter in my wrapper file to invert the reset gotten by the Logic Core IP block. But in Post implementation simulation - the behavior of the reset signal on both sides around this inverter is wierd. It is showing aresetn as the port of my wrapper - although aresetn is the port of IP block while areset is the port of my wrapper. Also, it shows that aresetn stays low during run - which probably means reset stays asserted.

How am I supposed to invert this reset signal polarity correctly ?

Thanks and sincerely

Bhawandeep Singh

[drjohnsmith]

do you mind posting were it says the reset polarity has changed please

[bhawandeepsingh]

https://www.xilinx.com/support/documentation/ip_documentation/div_gen/v5_1/pg151-div-gen.pdf - Page 42

and

https://www.xilinx.com/support/documentation/ip_documentation/xfft/v9_0/pg109-xfft.pdf - Page 89

[drjohnsmith]

Thanks for that,

I'd forgotten that resets used to be active high, and in the 'new' AXI land they are active low,

I'll have to keep an eye out for that , at least its documented.

As for the original question, 

   it should work just providing a reset externally of the correct polarity,

       can you share a code snippet please?

 Also , be aware, that signals get re named , and unless you have the keep attribute or equivalent, signals can be combined post place / route to make more efficient code by the tools.

[bhawandeepsingh]

The below is from my wrapper -

// Among the ports

input      areset;

// In the module body

reg aresetn;
always @ (posedge aclk)
    begin
        aresetn <= #0.1 ~areset;    
    end

//Instantiation of the LogicCore block
div_16_16_2clk_signed  zynq7_div_16_16_2clk_signed(
                                                .aclk(aclk),                                      // input wire aclk
                                                .aresetn(aresetn),                                // input wire aresetn

... and so on

[drjohnsmith]

Your syncronising the async reset to the clock , 

    do you need to do this ?

assign aresetn  = ~areset;

[bhawandeepsingh]

I did the same first.

It didnt work either, the original problem statement in first post of the thread is from combinational inversion.

It was exactly what you have written. The inverter was not showing.

Then I tried .arestn (!areset) in the instantiation - without specifying invertor/inversion separately.

Same behavior.

Then I put a flop. It is still not working. The module simulation is showing input lines stay at z although 2 of them are tied to 1 in RTL.

[drjohnsmith]

well, assuming the inverter has not been absorbed,

   and you are driving it correct, 

then sounds to me like your best bet is to take a step back and try a much simpler example ,

[bhawandeepsingh]

Much simpler example ?

We have a delivery coming ... I got to get this to work.

[hayk.petr · Accepted solution]

@bhawandeepsingh could you try this:

input areset;
reg aresetn;

always @ (posedge aclk or posedge areset)
	if (areset)
		aresetn <= 1'b0;
	else 
		aresetn <= 1'b1;
		

[bhawandeepsingh]

@hayk.petr- Thanks. The reset is getting inverted - and schematic matched verilog code. But for some reason, in some modules there is a 5-6 cycles delay b/w areset switching and aresetn switching in the post place and route simulation. I am still looking into it.  Thanks.