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Voyager
Voyager
3,422 Views
Registered: ‎06-24-2013

How to reset the FRAME_ECCE2 mechanism?

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I've written a short example which simulates the steps of frame error discovery and correction on 7 Series FPGAs. First, two consecutive frames with a single bit error are written via ICAPE2, then they are read back and the first bit error is properly detected and pinpointed by the FRAME_ECCE2 instance. This error is then corrected by simply overwriting the first faulty frame with a correct one and another read-back scan is performed. Unfortunately the second run, while reporting the correct syndrome, doesn't update the error location (i.e. the old error location is stuck in some way) as can be seen in the log.

 

Most likely there is some kind of reset required to prepare the FRAME_ECCE2 for the second scan, but as so often in this area, documentation is vague or simply not available.

 

Any on-topic input is appreciated!

Thanks in advance,

Herbert

-------------- Yes, I do this for fun!
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Xilinx Employee
Xilinx Employee
5,662 Views
Registered: ‎09-05-2007

The DSYNC sequence at the end of any transaction using ICAP will cause the Readback CRC scan to resume from the first frame in the device. If you look, you will see that the PicoBlaze reference design has a small circuit to detect the reading of frames and when the scan reaches the end of the device and wraps round. As well as using this to count the total number of frames in the scan of the device you could use this 'reference' to conduct your own experiments which confirm the 'reset' behaviour if that is so critical to you.  

Ken Chapman
Principal Engineer, Xilinx UK

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Scholar
Scholar
3,410 Views
Registered: ‎02-27-2008
H, please use the free SEM IP. We do not support error correction performed by any other method as it wastes far too much of our support resource. It is just to complex, so we offer the SEM IP. Use it.
Austin Lesea
Principal Engineer
Xilinx San Jose
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Voyager
Voyager
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Registered: ‎06-24-2013

Where can I find the HDL source for the SEM IP?

 

Thanks in advance,

Herbert

-------------- Yes, I do this for fun!
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Scholar
Scholar
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Registered: ‎02-27-2008

h,

 

We do not supply the source.  Again, it leads to endless support nonsense when it gets 'modified.'

 

It works, use it.  It is even beam tested in all possible modes.

 

What are doing?

 

Why are you doing it?

 

What is wrong with the proven, working, solution?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Voyager
Voyager
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Registered: ‎06-24-2013

We do not supply the source.  Again, it leads to endless support nonsense when it gets 'modified.'

Unfortunate.

 

What are doing?

Among other things, I'm developing FOSS/OH for the AXIOM Camera.

 

Why are you doing it?

Mainly because I can.

 

What is wrong with the proven, working, solution?

That it is closed source and thus I don't know what it does or how it impacts the system.

 

Hope that clarifies,

Herbert

-------------- Yes, I do this for fun!
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Xilinx Employee
Xilinx Employee
3,363 Views
Registered: ‎09-05-2007

PicoBlaze is provided with a reference design that can accesses the ICAP port in the 7-Series device (presented on the KC705 board). This design should appeal to anyone interested in configuration Readback CRC error detection and ECC correction. As I say in the documentation...

 

If you are at all concerned about Single Eventt Upsets (SEU) to configuration memory cells and the effect that they may have on a design then your primary interest should be the SEM IP core provided in with the Xilinx development tools and described in the ‘LogiCORE IP Soft Error Mitigation Controller Product Guide’ (pg036). Whilst the SEM IP core is recommended, the fundamental Readback CRC mechanism and single bit error correction capability is built-in to the silicon of every 7-Series device and the SEM IP core isn’t always required (see UG470). This reference design enables you to learn more about the built-in capabilities and evaluate how they work and how SEU may effect a design. Knowledge gained using this design will also be useful when the SEM IP core.

 

https://www.xilinx.com/products/intellectual-property/picoblaze.html

 

See 'design Files' tab and download the 'KCPSM6' package. In the zip file you will find a 'Reference Designs' folder and your initial interest will be the design in the 'ICAP' folder. The 'KC705_KCPSM6_ICAP_reference_design.pdf' describes the reference design and shows you exactly how PicoBlaze can be interfaced with ICAPE2 and monitor the Readback CRC using the FRAME_ECC2 primitives. The source code contained many comments and descriptions to aid your understanding and help you reuse it in your own applications.

 

 

Ken Chapman
Principal Engineer, Xilinx UK
Voyager
Voyager
3,356 Views
Registered: ‎06-24-2013

@chapman: Thanks a bunch!

 

For those digging out this thread in the future:

 

I figured out that the FRAME_ECCE2 mechanism automatically resets when the Frame Address Register (FAR) wraps around at the end of the last frame during background scan.

 

I'm not sure there is a way to explicitly reset the Mechanism but the fact that it works fine with the background scan is enough for my purpose.

 

Best,

Herbert

-------------- Yes, I do this for fun!
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Xilinx Employee
Xilinx Employee
5,663 Views
Registered: ‎09-05-2007

The DSYNC sequence at the end of any transaction using ICAP will cause the Readback CRC scan to resume from the first frame in the device. If you look, you will see that the PicoBlaze reference design has a small circuit to detect the reading of frames and when the scan reaches the end of the device and wraps round. As well as using this to count the total number of frames in the scan of the device you could use this 'reference' to conduct your own experiments which confirm the 'reset' behaviour if that is so critical to you.  

Ken Chapman
Principal Engineer, Xilinx UK

View solution in original post