01-10-2017 10:46 PM
In my design I want to use the GTGREFCLK in the JSED204_phy,I modified the CPLLREFCLKSEL to 3'b111,and drove the GTGREFCLK by MMCM(125MHz),but there were some errors when implementated the projection.
[DRC 23-20] Rule violation (REQP-52) connects_GTGREFCLK_ACTIVE - GTXE2_CHANNEL cell i_jesd204_0_support_block/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_0_phy_gt/inst/jesd204_0_phy_gt_i/gt0_jesd204_0_phy_gt_i/gtxe2_i: Use of the GTGREFCLK is reserved for test purposes only. This has the lowest performance of the available clocking methods and can degrade transceiver performance. Note that GTGREFCLK use may be caused by driving a REFCLK with a BUFG.
01-12-2017 12:44 AM
01-11-2017 04:26 AM
I just found that this IP core was not allowed to be modifyied.
when I open the Schematic in Sythesized Design,the CPLLREFCLKSEL[2:0] is still 1'b001.
How can I modify the CPLLREFCLKSEL ?
Thanks,
Bilkaka
01-11-2017 07:58 PM
Hi @bilkaka
Try these steps to change the setting:
Thanks,
Vinay
01-12-2017 12:44 AM