How to use GTGREFCLK in the IP core-JESD204_phy on K7?

[bilkaka]

In my design I want to use the GTGREFCLK in the JSED204_phy,I modified the CPLLREFCLKSEL to 3'b111,and drove the GTGREFCLK by MMCM(125MHz),but there were some errors when implementated the projection.

[DRC 23-20] Rule violation (REQP-52) connects_GTGREFCLK_ACTIVE - GTXE2_CHANNEL cell i_jesd204_0_support_block/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_0_phy_gt/inst/jesd204_0_phy_gt_i/gt0_jesd204_0_phy_gt_i/gtxe2_i: Use of the GTGREFCLK is reserved for test purposes only. This has the lowest performance of the available clocking methods and can degrade transceiver performance. Note that GTGREFCLK use may be caused by driving a REFCLK with a BUFG.

[bilkaka]

I just found that this IP core was not allowed to be modifyied.

when I open the Schematic in Sythesized Design,the CPLLREFCLKSEL[2:0] is still 1'b001.

How can I modify the CPLLREFCLKSEL ?

Thanks,

Bilkaka

[vuppala]

Hi @bilkaka

Try these steps to change the setting:

1. Open Synthesized design
2. Select the GT in the schematic
3. In Properties window, look for CPLLREFCLKSEL and change its value.

Thanks,

Vinay

[bilkaka · Accepted solution]

Hi @vuppala
Thanks for your advice.
I set up the IP core again.
"shared logic in example design",
and in the Synthesis Options , I chose Global.
Then it can be modified.

Thanks,
Bilkaka