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Observer tamzid
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Registered: ‎12-29-2015

ICAPE2 Configuration Readback issue Zynq 7Z010

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Hi,
I am trying to do a readback of the configuration bitstream using ICAPE2 primitive in the Zybo board. I have created a state machine that sends:

 CE (icap_ceRegNext), //0 means enable

RDWR(icap_writeRegNext),  //0 means write mode, 1 means read mode

32 bit data in (icap_data_inRegNext),

 and receives 32 bit data out (icap_data_outRegNext).

Ignore the data_valid signal as it is generated by me. (kindly refer to the figures)


Through the icap_data_inRegNext bus, I have written the configuration commands for reading back certain number of frames back from the configuration memory (see figure Part 1 and 2) .  The configuration commands are written according to  ug470  (page 126). https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

 

Now my question is, even after applying the commands, why the config memory data is not coming out through icap_data_outRegNext bus? I am expecting the frames to appear when stateReg[5:0] =31 (in part 3). But the icap output is fixed at FFD9FFFF.

 

Please note that icap_data_inRegNext and icap_data_outRegNext are Bit Swapped before being connected to ICAPE2 primitive  as instructed in ug470. Also the jumpers are switched away from JTAG mode before loading the design. 

 

Any suggestion to find the mistake would be appreciated. Thanks
 

Part 1

image.png

 

 

 

Part 2

image (1).png

 

Part3

image (2).png

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Xilinx Employee
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Registered: ‎09-05-2007

Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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@tamzid

This is irritating me as much as you so today I grabbed your code (from your last posting) and added into a PicoBlaze design that I'm using to run experiments on a Spartan-7 device (XC7S50). I tried to leave your code alone as much as possible especially in the actual ICAPE2 interface and reader state machine. I removed the 'clk_wiz' and connect everything my 100MHz system clock. I removed the ILA and made connections that PicoBlaze could observe.

 

I added registers to capture the lower 8-bits of the data coming out of ICAP on successive clock cycles.... 

 

--Read will start from next clock

when 8 => data <= x"20000000";

cs_l <= '0'; r_wx <= '1';--Assert CE -- read Clock 1 

 

when 9 => data <= x"20000000"; -- read Clock 2

cs_l <= '0'; r_wx <= '1';

idcode1 <= data_out(7 downto 0);

 

when 10 => data <= x"20000000"; -- read Clock 3

cs_l <= '0'; r_wx <= '1';

idcode2 <= data_out(7 downto 0);

 

when 11 => data <= x"20000000"; -- read Clock 4

cs_l <= '0'; r_wx <= '1';

idcode3 <= data_out(7 downto 0);

 

when 12 => data <= x"20000000"; -- read Clock 5

cs_l <= '0'; r_wx <= '1';

idcode4 <= data_out(7 downto 0);

 

I first proved that my 4 registers contained zero and that your state machine wasn't active (RIP=0). Then I triggered your state machine and saw that RIP went High. Given that your code never terminates state machine and it spins round and round forever that was a one-shot event! Anyway, the four registers then contained  DB, DB, 00 and 93 indicating that IDCODE was indeed read from ICAPE2 and was captured during what you have called 'read clock 5' (the IDCODE of my device is X362F093).

So on the basis that your code works the issue must be related to either to some of your XDC constraints (I suggest you remove anything you don't absolutely need as my XDC file is pretty much only I/O pin and clock definitions) or whatever is configuring your device is not completing and letting go in a way that prevents ICAPE2 from being able to be accessed. It's a bit of a pain but try programming your Flash and booting in master mode so the FPGA is in charge.

 

@hpoetzl

Ok, I stand corrected, the NOOP's were not vital in this arrangement. On reflection, I recall noticing differences depending on whether the ICAP enable was pulsed (i.e. for one clock cycle at a time) rather than active for continuous cycles and/or combined with a free running clock or individual clock pulses. In other words, the ICAP enable does not truly act as a global clock enable and in the extremely controlled case you need the NOOPs to 'create' the clock cycles to propagate the ICAP state machine. Did you know that ICAP is one of the classes taught at Hogwarts?

 

 

Ken Chapman
Principal Engineer, Xilinx UK
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Xilinx Employee
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Hi @tamzid

 

The first 101 words are a dummy frame.

 

Thanks

Simon

 

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Xilinx Employee
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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PicoBlaze is provided with a reference design that can accesses the ICAP port in the 7-Series device (presented on the KC705 board). This design includes reading and writing of individual configuration frames.

 

https://www.xilinx.com/products/intellectual-property/picoblaze.html

 

See 'design Files' tab and download the 'KCPSM6' package. In the zip file you will find a 'Reference Designs' folder and your initial interest will be the design in the 'ICAP' folder. The 'KC705_KCPSM6_ICAP_reference_design.pdf' describes the reference design and shows you exactly how PicoBlaze can be interfaced with ICAPE2 and monitor the Readback CRC using the FRAME_ECC2 primitives. The source code contained many comments and descriptions to aid your understanding of the mechanisms when implementing your own designs or to help you reuse this reference in your own applications.

Ken Chapman
Principal Engineer, Xilinx UK
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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@tamzid:

 

I didn't find any HDL code, so I'm guessing here what might go wrong:

 

First, FFD9FFF still seems wrong, as the correctly swapped ICAPE2 output will be FFFFFFD9.

Secondly, you need to read at least two frames to get one valid frame, as the first frame is a dummy and will be empty.

Finally when you still get the status output (FFFFFFD9) during read-back from the ICAPE2, something is likely wrong with the timing.

 

It would help to see the HDL code in question or VCD data including the clock.

 

Hope that helps,

Herbert

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Observer tamzid
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Hi  

 

 

First, FFD9FFF still seems wrong, as the correctly swapped ICAPE2 output will be FFFFFFD9.

>> Tamzid: Let me see if I have made any mistake in swapping. 

 

Secondly, you need to read at least two frames to get one valid frame, as the first frame is a dummy and will be empty.

>> Tamzid: Are you talking about the first 101 dummy frames? After reaching the readmode, I made the FSM to read 255 numbers of frames. This number is also mentioned when I provide my desired number of frames to be read. By writing 32'h480000FF;  in state STATE_STEP8_WORD2. Is there something else?

 

 

 

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Observer tamzid
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Hi @simon,
Yes. But I have asserted the read for 255 frames. And the data was stuck in the same value throughout the end. 

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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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@tamzid:

 

A frame on 7 Series consists of 101 32bit words.

 

I've written a small example which writes a frame and reads back two frames via ICAPE2, which might help you.

 

The serial output shows you the ICAPE2 input and output as well as the CSIB and RDWRB states.

 

Best,

Herbert

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Observer tamzid
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Hi @hpoetzl

Thanks for the example code. 

 

The first 2 column in the  output is 32 bit input to and output from the  ICAP. But what does the 3rd  and 4th column shows? Are these also output from ICAP? And where are the single bit CSIB and RDWRB states? 

 

 

out.JPG

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Xilinx Employee
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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It looks like you are not opening communications so ICAP is staying 'closed' and not telling you anything. Looking at your 'swapping' it appears you have correctly swapped the bits within each byte but have incorrectly swapped the bytes within the word.

 

Personally speaking, I always found it best to read the device ID first as it is a known value of one word. You can even simulate that one (hence the DEVICE ID string on the ICAPE2 primitive). Once you can read that you at least know that your basic communication with ICAP is working before doing the tricky stuff like reading configuration memory.

 

Even if you ignore my PicoBlaze reference design code I still think you would get something out of looking at the diagram on page 6 of the 'KC705_KCPSM6_ICAP_reference_design.pdf' document. That shows you the relative timing of ICAP inputs and outputs so you capture information on the correct clock cycle (that becomes critical when reading streams of data rather than individual registers).

Ken Chapman
Principal Engineer, Xilinx UK
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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@tamzid

 

The first hex nibble (left to right) of the third 32bit block contains the CSIB (0x8) and the RDWRB (0x4) from the ICAPE2. The remaining data is from the FRAME_ECCE2 which I was originally investigating.

 

Here is the full 128bit vector:

rev_f(I) & rev_f(O) & CSIB & RDWRB & "00" & "00" & FAR & "000" & SYNDROME & SYNWORD & SYNBIT & CRCERROR & ECCERRORSINGLE & ECCERROR & SYNDROMEVALID;

 

Hope that helps,

Herbert

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Observer tamzid
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Hi @chapman

You are right. My Swapping was wrong. Therefore I corrected it. But the issue is still there. 

 

I also felt that I should start with something basic as you said. So I went back and changed my code to read the IDCODE. 

 

However, the issue is the same. My readback data is halted in FFFFFFD9. Both code and ILA outputs are attached. I designed the state machine to work according the following approach of reading IDCODE. 

https://forums.xilinx.com/t5/Configuration/Can-not-read-IDCODE-from-ICAPE2/td-p/648626

 

However Im not sure how long I should wait in the reading mode. 

 

I want to make my code work for the IDCODE first, before I move onto more complex task. If you could suggest something based on my code that would be helpful. 

 

I am looking at the picoblaze example, but initially I felt there are too much information compared to what I can manage right now.  I appreciate your help. 

IDCODE RD.JPG
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Good decision to start with something simple!

 

I made your FSM a module with ports for the ICAPE2 and used it to drive my example.

The generated sequence is this:

 

00000000.FFFFFFD9.8
00000000.FFFFFFD9.0
FFFFFFFF.FFFFFFD9.0
000000BB.FFFFFFD9.0
11220044.FFFFFFD9.0
FFFFFFFF.FFFFFFD9.0
AA995566.FFFFFFD9.0
20000000.FFFFFFD9.0

 

00000000.FFFFFFDB.C
00000000.FFFFFFDB.4
00000000.FFFFFFDB.4
00000000.FFFFFFDB.8
00000000.FFFFFFDB.0

 

30008001.FFFFFFDB.0
0000000D.FFFFFFDB.0
20000000.FFFFFFDB.0
00000000.FFFFFFDB.8
00000000.FFFFFFD9.0

 

Which would be basically fine if you'd send the Read command 28018001 first before changing the direction.

 Here a working sequence for comparison:

 

FFFFFFFF.FFFFFFD9.0
AA995566.FFFFFFD9.0
20000000.FFFFFFD9.0


28018001.FFFFFFDB.0
20000000.FFFFFFDB.C
20000000.FFFFFFDB.4
20000000.FFFFFFDB.4

 

30008001.FFFFFFDB.0
0000000D.0362D093.0
20000000.FFFFFFD1.0
20000000.FFFFFFD1.0
20000000.FFFFFFD1.0
20000000.FFFFFFD9.0

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
Xilinx Employee
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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As Herbert has already indicated, you won’t get anything out of ICAP until you ask for something so you do need that IDCODE register read instruction (28018001).

 

As your design instantiated ICAPE2 with the bus width defined to be 32 bits you do not need to include 000000BB and 11220044 in your sequence.

 

Ken Chapman
Principal Engineer, Xilinx UK
Observer tamzid
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Dear @hpoetzl , @chapman

 

Thanks a lot for breaking down the things for me. I was travelling last week and was hopeful  seeing  @hpoetzl 's output  on the IDCODE. 

Unfortunately, I tried the exact same sequence as described to read the IDCODE and the output is fixed at FFFFFFD9. I am not sure if you guys will find any mistake on the code. I think the mistake could be in somewhere else. 

 

Since it was mentioned that code here works for readback and write. I went ahead and implemented it on zybo, In Zynq the ICAP can run at 100 MHZ, but in this design the clock to ICAP is much slower. But I did not change anything. I hope slower is OK.

 

I had to add a  single bit primary input (named reset) as a trigger mechanism  for  the ILA . Otherwise its exactly same code. The resultant Output is in ILA.JPG. The expected.JPG states what it should provide if things go well. We can see that, output should change from FFFFFFD9 to FFFFFFDB. But it is still stuck at FFFFFFD9 in my implementation, as shown in ILA.JPG. :(



I have attached the code (icape2.vhd) and the xdc file. I would appreciate any indication to understand the problem. 

ILA.JPG
expected.JPG
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Xilinx Employee
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Your latest waveforms only appear to show write commands being send to ICAP so again we wouldn't expect anything to come out! I suggest you stick to just trying to read IDCODE first. 

Ken Chapman
Principal Engineer, Xilinx UK
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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In Zynq the ICAP can run at 100 MHZ, but in this design the clock to ICAP is much slower.

But I did not change anything. I hope slower is OK.

 

My examples all run with ICAP clock below 100kHz, so I guess slow is fine.

 

Best,

Herbert

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Observer tamzid
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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@chapman, OK, thanks. But do you know why the output changes from FFFFFFD9 to FFFFFFDB in the expected one? I thought if there is any communication with ICAP, this would happen to my ICAP output also. Because its the same code as @hpoetzl gave. 

 

@hpoetzl in your code, before generating the bitstream you used the following tcl commands. Are these essential for any readback attempt? I am trying to see if any of my implementation options are conflicting with readback. I usually execute with default synthesis, implementation and bit gen settings. But while running yours I used the following ones. 

set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.GENERAL.COMPRESS False [current_design]
set_property BITSTREAM.GENERAL.CRC "DISABLE" [current_design]
set_property BITSTREAM.CONFIG.USERID "DEADC0DE" [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS "00000000" [current_design]
set_property BITSTREAM.READBACK.ACTIVERECONFIG Yes [current_design]

write_bitstream -raw_bitfile -readback_file -bin_file -force $ODIR/icap


   

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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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@tamzid

 

None of those commands are critical for readback (which can be easily verified by simply commenting them out ... except for the write_bitstream of course).

 

Best,

Herbert

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Observer tamzid
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Hi @hpoetzl, do you know why in your provided code output, the ICAP output changed from FFFFFFD9 to FFFFFFDB? As I am told now, I should not expect anything to change. Just wanted to ensure this before I go back to IDCODE example. 

 

 

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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Hey @tamzid

 

do you know why in your provided code output, the ICAP output changed from FFFFFFD9 to FFFFFFDB?

 

Well, the output of the ICAPE2 is not documented at all (as far as I know, input welcome). That said, my best guess is that it's some kind of status output during write operations, and bit 1 (difference between 'B' and '9') reflects whether the ICAP is synchronized or not (SYNC vs DESYNC status). So basically when you send the SYNC word (AA995566), bit 1 becomes active and when you send the DESYNC command (300080010000000D) it becomes inactive again.

 

The designs out there using the ICAPE2 (like for example KCPSM6 referenced by @chapman) only latch the ICAPE2 output when there is expected output (i.e. 3 cycles after CSIB goes low), so it won't be visible on those.

 

As I am told now, I should not expect anything to change.

 

I don't think you will get anything useful out of the ICAPE2 as long as this status bit is not set.

 

Hope that helps,

Herbert

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Observer tamzid
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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I see. I am observing ICAP2 output all the time using ILA. Thus I should expect to see the change from '9' to 'B' in ILA probe. This SYNC vs DESYNC change is more basic than reading back from registers. This makes me inclined to think that I am missing a certain implementation option that is key in communicating with ICAP. I am not sure if the default implementation settings. I use the default VIVADO 2015.2 settings for synthesis, implementation and bit gen. And the mode pins are switched to non-JTAG mode. If you thing there is something else to be changed please let me know. 

 

 

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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Please don't take what I am about to say as the letter of the law but I think the ICAP output somewhat mimics the SelectMAP port. As such, a look at Table 2-12 on page 49 of UG470 could be a clue. If it is, then the difference between D9 and DB hex would correlate with the DALIGN bit (D06) changing state to reflect when a SYNC word has been received. If this is true then it looks like an ICAP transaction is starting but with no valid read commands nothing else if coming out yet (or is being missed beyond where we are shown in the waveforms).

 

 By the way, my PicoBlaze reference design doesn't contain any special constraints; it just works!

Ken Chapman
Principal Engineer, Xilinx UK
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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@tamzid

 

When your ICAP output stays at FFFFFFD9 all the time, then I would suggest to double and triple check the bit swapping on the input (maybe attach a probe directly to the ICAP and check for the SYNC word).

 

When you do not get FFFFFFD9 at all, then something else might be off (for example the ICAP seems to need some time to get ready, which is also reflected in those status bits).

 

Best,

Herbert

 

PS: I would also suggest to hand out some kudos for all that valuable input you received ...

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Observer tamzid
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Hi all,
I was able to see the IDCODE in simulation :) . (please see "data out" in yellow near count =11 in Sim.jpg) 

 

However when mapped in the device, the IDCODE did not appear (see ILA.jpg)

 

The clock to ICAPE2 is 10 MGZ. Codes are attached as well. If you guys have any thought on  why it did not appear please let me know.

 

 Its better than before since it at least works in simulation, thanks a lot for answering so many questions and providing feedback! But I have a long way to go I believe. 

 

For behavioral simulation of the  configuration readback, I have seen that a ".rbt" file is used during ICAPE2 instantiation. Where this .rbt file should be placed so that the simulator can locate it? I mean in which folder?
For generating ".rbt" I believe this should be followed. 

 

 

 

 

 

at 

 

Sim.JPG
ILA.JPG
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Congrat @tamzid!

 

I wouldn't waste much time on behavioral simulation, according to @austin "Simulation of such complex behavior is not done" (from the other thread).

 

Best,

Herbert

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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Hi @tamzid

 

You can place it in the source folder:

https://www.xilinx.com/support/answers/53632.html

 

Thanks

Simon

Thanks
Simon
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Xilinx Employee
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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The simulation of reading IDCODE is promising; at least that means you now have the bits all twisted the right way.

 

I'm wondering if there is an issue accessing ICAP in the physical device either because JTAG is being used or the configuration process hasn't fully completed for some reason. Only one thing can access configuration at a time and JTAG has highest priority. There shouldn't be an issue using ILA and ICAP at the same time. What have you go the mode pins set to? If they are set to JTAG then try changing them to something else (that won't stop you configuring via JTAG). If you do change the mode pins then make sure you cycle the power to be sure that the device wakes up and reads them in the non-JTAG mode. This is only a guess on my part but worth checking/trying. 

Ken Chapman
Principal Engineer, Xilinx UK
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Hi @tamzid,

 

You can refer to Multiboot module and compare them. I remember I can readback frame after slightly modifying this module.

 

Thanks

Simon

Thanks
Simon
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Observer tamzid
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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Hi @chapman

Yes this was my initial confusion that is my use of ILA is coming on the way of ICAP. But in this post, I was assured that Its OK. 
Right now, I restart the board before every reprogram. And mode pins are always set to SD card, instead of JTAG.

But I use JTAG to program. As you said, programming through JTAG is still available. I would wait for few seconds to ensure the configuration has ended. 

 

 

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Re: ICAPE2 Configuration Readback issue Zynq 7Z010

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Why are you using two clocks? Ok, it should work but I'm not entirely comfortable and when something isn't working as intended I'd keep things nice and simple and totally synchronous to rule anything silly out.

 

Something else to try....

  

#

# Force ICAPE2 to the required (top) site in the device.

#

set_property LOC ICAP_X0Y1 [get_cells ICAPE2_inst]

#

 

I have that in my PicoBlaze reference design. If your device also has more than one ICAPE2 site then the top one is active first.

Ken Chapman
Principal Engineer, Xilinx UK