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parvathy.punnappurath
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Registered: ‎06-13-2018

IOB not inferring

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Hi,

The device I'm using is zynq 7000 series family in Vivado 2017.2
I have been trying to infer IOB for an inout port . But as mentioned in AR# 62661 the IOB is not inferred in report_datasheet .
I have added the IOB attribute in RTL (* IOB = "TRUE" *) and also in xdc file (set_property IOB TRUE [get_ports  ] )
None of this worked.
Then I tried adding IOB to the registers as well .. still not inferring IOB.

Could someone help with this please ?

 

Thank you,

Parvathy

 

 

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dpaul24
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Registered: ‎08-07-2014

Doesn't that IOB is not inferred ?

1st - Please change your terminology. An IOB is *never* inferred. A flop/FDRE in an IOB is inferred.

 

Yes that's the smartest way.

 

Otherwise cross-checking can be done by opening the implemented design, zooming into that IOB and checking out if a flop(FDRE) is present there or not.

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hongh
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Hi, @parvathy.punnappurath ,
I don't think the your topic is accurate.
IOB always exists and it is not inferred. The IOB attribute is trying to place the register into IOB.
Please show more detailed information or provide your opt.dcp for analysis.

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dpaul24
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@parvathy.punnappurath,

 

What Hong says is absolutely correct.

I have been trying to infer IOB for an inout port . - whatever your top-level port type is, it is going through an IOB.

 

Read this to understand why an IOB constraint is used - https://forums.xilinx.com/t5/Virtex-Family-FPGAs/Why-need-to-use-IOB-constraint/td-p/101486

 

I suspect that you are not connecting your inout port properly to a tri-state buffer.

In the absence of other meaningful info, this is my speculation. 

 

 

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parvathy.punnappurath
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Hi

 

Thank you @hongh and @dpaul24 for your prompt response

 

I'll give a  description of what I'm trying to achieve.

 

I have an inout data port , which I'm trying to place to IOB.

 

I have come across several forums stating that IOB attribute could be set for ports as well as registers

 

Even after adding the attribute to the port, IOB is not inferred. (referred report_datasheet)

@dpaul24 I have added a tristate buffer.

 

Thank you,

Parvathy

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dpaul24
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I have come across several forums stating that IOB attribute could be set for ports...

Show us.....

 

Coming back...

 

None of this worked.

What happens if you don't put the IOB constraint?

 

Then I tried adding IOB to the registers as well .. still not inferring IOB.

Could someone help with this please ?

Can you please tell us what the actual problem is? Why do you want to put the IOB constraint to a port?

Critical warnings, timing errors, etc?

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parvathy.punnappurath
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Hi @dpaul24

 

Please refer the below mentioned link for

"I have come across several forums stating that IOB attribute could be set for ports...Show us..."

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug912-vivado-properties.pdf#page=230

 

To clarify, I have registered the tri state buffer output enable signal.

 

"Why do you want to put the IOB constraint to a port?"

I have timing issues.. So I wanted to check the "Max clk edge to port delay " column in "output ports to clock-out" option in "report_datasheet" to know how it varies if its not placed in IOB , if ILA is there etc.

 

PS : Please note that I'm using vivado 2017.2

 

Thank you,

Parvathy

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dpaul24
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Yes, as said in the doc, you place the constraint on the port but what actually takes place is that the register connected to that port is placed on a IOB. This has been told by @hongh to you initially.

 

To clarify, I have registered the tri state buffer output enable signal.

And you want to place this register at IOB?

 

Note that tri-state-buffers are always placed at IOBs.

Generally speaking, for tri-state-buffers, you have _i, _o and _t signals. You can place registers for the _i (immediately after) and _o (immediately after) at the IOB by using constraints. Theoretically for the _t signal a reg can also be placed but I have not come across any design doing so.

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parvathy.punnappurath
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Hi @dpaul24

 

As per AR #62661 https://www.xilinx.com/support/answers/62661.html, to check whether IOB is inferred, one has to check the report_datasheet . In the IO reg type, if IOB is inferred, something like FDRE (IOB) will be there. In my report_datasheet this (IOB) is not coming , even after placing the attribute onto the port. Doesn't that IOB is not inferred ?

 

Thank you,

Parvathy

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dpaul24
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Doesn't that IOB is not inferred ?

1st - Please change your terminology. An IOB is *never* inferred. A flop/FDRE in an IOB is inferred.

 

Yes that's the smartest way.

 

Otherwise cross-checking can be done by opening the implemented design, zooming into that IOB and checking out if a flop(FDRE) is present there or not.

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parvathy.punnappurath
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Hi @dpaul24

 

"flop/FDRE in an IOB is inferred"

Ok

 

" checking out if a flop(FDRE) is present "

 

FDRE is present.

 

Does that mean  flop in an IOB is inferred  ?

 

Thank you,

Parvathy

 

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