UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor fuxx_14
Visitor
275 Views
Registered: ‎03-22-2018

ISERDES clocking in oversample mode

Hi, 
when using a MMCM to create the 4 clocks needed for OVERSAMPLE mode of ISERDESE2, we get a partial routed error with no further explanation in Vivado 2017.3.1.

We use following clocking structure:
 MMCM -> CLKOUT0 for  CLK, CLKB of ISERDESE2, connected via BUFIO
 MMCM -> ClKOUT1  for OCLK / OCLKB of ISERDESE2, connected via BUFIO

Do we have to connect ISERDESE2 in another way?

0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
243 Views
Registered: ‎06-13-2018

Re: ISERDES clocking in oversample mode

Hi @fuxx_14 :

CLK and CLKB are driven by a BUFIO. OCLK and OCLKB are driven by a BUFIO which should be phase shifted by 90°. The two BUFIOs should be driven from a single MMCM.

Can you share your clocking topology screenshot here?

What is the error you are getting? Share the log file as well.

 

Thanks,

Priyanka

 

 

0 Kudos
Visitor fuxx_14
Visitor
219 Views
Registered: ‎03-22-2018

Re: ISERDES clocking in oversample mode

We exactly used that clocking topology. The routing error is caused by using the BUFIO clocks which are also used as shift clock (ISERDESE2 outputs are driven by CLK), but BUFIO cannot drive CLBs.
So we tried to shift the 4bit ISERDESE2 output data in order to get a parallel bus of oversampled data.

So how should we get the oversampled data?
Using two BUFGs instead of two BUFIOs for clocking? Are there further recommendations?

Thanks

0 Kudos